From owner-svn-src-head@FreeBSD.ORG Sun Apr 21 13:31:56 2013 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.FreeBSD.org [8.8.178.115]) by hub.freebsd.org (Postfix) with ESMTP id 1BAAB9DD; Sun, 21 Apr 2013 13:31:56 +0000 (UTC) (envelope-from kib@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) by mx1.freebsd.org (Postfix) with ESMTP id F13E91379; Sun, 21 Apr 2013 13:31:55 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.6/8.14.6) with ESMTP id r3LDVt5X006266; Sun, 21 Apr 2013 13:31:55 GMT (envelope-from kib@svn.freebsd.org) Received: (from kib@localhost) by svn.freebsd.org (8.14.6/8.14.5/Submit) id r3LDVt6c006264; Sun, 21 Apr 2013 13:31:55 GMT (envelope-from kib@svn.freebsd.org) Message-Id: <201304211331.r3LDVt6c006264@svn.freebsd.org> From: Konstantin Belousov Date: Sun, 21 Apr 2013 13:31:55 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r249724 - in head/lib/msun: . amd64 i387 x86 X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 21 Apr 2013 13:31:56 -0000 Author: kib Date: Sun Apr 21 13:31:55 2013 New Revision: 249724 URL: http://svnweb.freebsd.org/changeset/base/249724 Log: Merge the 386 and amd64 versions of the fenv.h, to make cc -m32 compilations which use fenv.h work. Reviewed by: tjil Sponsored by: The FreeBSD Foundation Added: head/lib/msun/x86/ head/lib/msun/x86/fenv.h - copied, changed from r249723, head/lib/msun/i387/fenv.h Deleted: head/lib/msun/amd64/fenv.h head/lib/msun/i387/fenv.h Modified: head/lib/msun/Makefile Modified: head/lib/msun/Makefile ============================================================================== --- head/lib/msun/Makefile Sun Apr 21 12:16:59 2013 (r249723) +++ head/lib/msun/Makefile Sun Apr 21 13:31:55 2013 (r249724) @@ -35,6 +35,10 @@ CFLAGS+= -I${.CURDIR}/ld128 .PATH: ${.CURDIR}/src .PATH: ${.CURDIR}/man +.if ${MACHINE_CPUARCH} == "i386" || ${MACHINE_CPUARCH} == "amd64" +.PATH: ${.CURDIR}/x86 +.endif + LIB= m SHLIBDIR?= /lib SHLIB_MAJOR= 5 Copied and modified: head/lib/msun/x86/fenv.h (from r249723, head/lib/msun/i387/fenv.h) ============================================================================== --- head/lib/msun/i387/fenv.h Sun Apr 21 12:16:59 2013 (r249723, copy source) +++ head/lib/msun/x86/fenv.h Sun Apr 21 13:31:55 2013 (r249724) @@ -36,26 +36,6 @@ #define __fenv_static static #endif -/* - * To preserve binary compatibility with FreeBSD 5.3, we pack the - * mxcsr into some reserved fields, rather than changing sizeof(fenv_t). - */ -typedef struct { - __uint16_t __control; - __uint16_t __mxcsr_hi; - __uint16_t __status; - __uint16_t __mxcsr_lo; - __uint32_t __tag; - char __other[16]; -} fenv_t; - -#define __get_mxcsr(env) (((env).__mxcsr_hi << 16) | \ - ((env).__mxcsr_lo)) -#define __set_mxcsr(env, x) do { \ - (env).__mxcsr_hi = (__uint32_t)(x) >> 16; \ - (env).__mxcsr_lo = (__uint16_t)(x); \ -} while (0) - typedef __uint16_t fexcept_t; /* Exception flags */ @@ -84,18 +64,32 @@ typedef __uint16_t fexcept_t; #define _SSE_ROUND_SHIFT 3 #define _SSE_EMASK_SHIFT 7 -__BEGIN_DECLS +#ifdef __i386__ +/* + * To preserve binary compatibility with FreeBSD 5.3, we pack the + * mxcsr into some reserved fields, rather than changing sizeof(fenv_t). + */ +typedef struct { + __uint16_t __control; + __uint16_t __mxcsr_hi; + __uint16_t __status; + __uint16_t __mxcsr_lo; + __uint32_t __tag; + char __other[16]; +} fenv_t; +#else /* __amd64__ */ +typedef struct { + struct { + __uint32_t __control; + __uint32_t __status; + __uint32_t __tag; + char __other[16]; + } __x87; + __uint32_t __mxcsr; +} fenv_t; +#endif /* __i386__ */ -/* After testing for SSE support once, we cache the result in __has_sse. */ -enum __sse_support { __SSE_YES, __SSE_NO, __SSE_UNK }; -extern enum __sse_support __has_sse; -int __test_sse(void); -#ifdef __SSE__ -#define __HAS_SSE() 1 -#else -#define __HAS_SSE() (__has_sse == __SSE_YES || \ - (__has_sse == __SSE_UNK && __test_sse())) -#endif +__BEGIN_DECLS /* Default floating-point environment */ extern const fenv_t __fe_dfl_env; @@ -114,6 +108,68 @@ extern const fenv_t __fe_dfl_env; #define __ldmxcsr(__csr) __asm __volatile("ldmxcsr %0" : : "m" (__csr)) #define __stmxcsr(__csr) __asm __volatile("stmxcsr %0" : "=m" (*(__csr))) +int fegetenv(fenv_t *__envp); +int feholdexcept(fenv_t *__envp); +int fesetexceptflag(const fexcept_t *__flagp, int __excepts); +int feraiseexcept(int __excepts); +int feupdateenv(const fenv_t *__envp); + +__fenv_static inline int +fegetround(void) +{ + __uint16_t __control; + + /* + * We assume that the x87 and the SSE unit agree on the + * rounding mode. Reading the control word on the x87 turns + * out to be about 5 times faster than reading it on the SSE + * unit on an Opteron 244. + */ + __fnstcw(&__control); + return (__control & _ROUND_MASK); +} + +#if __BSD_VISIBLE + +int feenableexcept(int __mask); +int fedisableexcept(int __mask); + +/* We currently provide no external definition of fegetexcept(). */ +static inline int +fegetexcept(void) +{ + __uint16_t __control; + + /* + * We assume that the masks for the x87 and the SSE unit are + * the same. + */ + __fnstcw(&__control); + return (~__control & FE_ALL_EXCEPT); +} + +#endif /* __BSD_VISIBLE */ + +#ifdef __i386__ + +/* After testing for SSE support once, we cache the result in __has_sse. */ +enum __sse_support { __SSE_YES, __SSE_NO, __SSE_UNK }; +extern enum __sse_support __has_sse; +int __test_sse(void); +#ifdef __SSE__ +#define __HAS_SSE() 1 +#else +#define __HAS_SSE() (__has_sse == __SSE_YES || \ + (__has_sse == __SSE_UNK && __test_sse())) +#endif + +#define __get_mxcsr(env) (((env).__mxcsr_hi << 16) | \ + ((env).__mxcsr_lo)) +#define __set_mxcsr(env, x) do { \ + (env).__mxcsr_hi = (__uint32_t)(x) >> 16; \ + (env).__mxcsr_lo = (__uint16_t)(x); \ +} while (0) + __fenv_static inline int feclearexcept(int __excepts) { @@ -150,9 +206,6 @@ fegetexceptflag(fexcept_t *__flagp, int return (0); } -int fesetexceptflag(const fexcept_t *__flagp, int __excepts); -int feraiseexcept(int __excepts); - __fenv_static inline int fetestexcept(int __excepts) { @@ -168,21 +221,6 @@ fetestexcept(int __excepts) } __fenv_static inline int -fegetround(void) -{ - __uint16_t __control; - - /* - * We assume that the x87 and the SSE unit agree on the - * rounding mode. Reading the control word on the x87 turns - * out to be about 5 times faster than reading it on the SSE - * unit on an Opteron 244. - */ - __fnstcw(&__control); - return (__control & _ROUND_MASK); -} - -__fenv_static inline int fesetround(int __round) { __uint32_t __mxcsr; @@ -206,9 +244,6 @@ fesetround(int __round) return (0); } -int fegetenv(fenv_t *__envp); -int feholdexcept(fenv_t *__envp); - __fenv_static inline int fesetenv(const fenv_t *__envp) { @@ -231,28 +266,89 @@ fesetenv(const fenv_t *__envp) return (0); } -int feupdateenv(const fenv_t *__envp); +#else /* __amd64__ */ -#if __BSD_VISIBLE +__fenv_static inline int +feclearexcept(int __excepts) +{ + fenv_t __env; -int feenableexcept(int __mask); -int fedisableexcept(int __mask); + if (__excepts == FE_ALL_EXCEPT) { + __fnclex(); + } else { + __fnstenv(&__env.__x87); + __env.__x87.__status &= ~__excepts; + __fldenv(__env.__x87); + } + __stmxcsr(&__env.__mxcsr); + __env.__mxcsr &= ~__excepts; + __ldmxcsr(__env.__mxcsr); + return (0); +} -/* We currently provide no external definition of fegetexcept(). */ -static inline int -fegetexcept(void) +__fenv_static inline int +fegetexceptflag(fexcept_t *__flagp, int __excepts) +{ + __uint32_t __mxcsr; + __uint16_t __status; + + __stmxcsr(&__mxcsr); + __fnstsw(&__status); + *__flagp = (__mxcsr | __status) & __excepts; + return (0); +} + +__fenv_static inline int +fetestexcept(int __excepts) { + __uint32_t __mxcsr; + __uint16_t __status; + + __stmxcsr(&__mxcsr); + __fnstsw(&__status); + return ((__status | __mxcsr) & __excepts); +} + +__fenv_static inline int +fesetround(int __round) +{ + __uint32_t __mxcsr; __uint16_t __control; + if (__round & ~_ROUND_MASK) + return (-1); + + __fnstcw(&__control); + __control &= ~_ROUND_MASK; + __control |= __round; + __fldcw(__control); + + __stmxcsr(&__mxcsr); + __mxcsr &= ~(_ROUND_MASK << _SSE_ROUND_SHIFT); + __mxcsr |= __round << _SSE_ROUND_SHIFT; + __ldmxcsr(__mxcsr); + + return (0); +} + +__fenv_static inline int +fesetenv(const fenv_t *__envp) +{ + /* - * We assume that the masks for the x87 and the SSE unit are - * the same. + * XXX Using fldenvx() instead of fldenv() tells the compiler that this + * instruction clobbers the i387 register stack. This happens because + * we restore the tag word from the saved environment. Normally, this + * would happen anyway and we wouldn't care, because the ABI allows + * function calls to clobber the i387 regs. However, fesetenv() is + * inlined, so we need to be more careful. */ - __fnstcw(&__control); - return (~__control & FE_ALL_EXCEPT); + __fldenvx(__envp->__x87); + __ldmxcsr(__envp->__mxcsr); + return (0); } -#endif /* __BSD_VISIBLE */ +#endif /* __i386__ */ __END_DECLS