From owner-svn-src-head@freebsd.org Sun Jul 10 01:09:18 2016 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 0A219B8332E; Sun, 10 Jul 2016 01:09:18 +0000 (UTC) (envelope-from mav@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id B37F31A3F; Sun, 10 Jul 2016 01:09:17 +0000 (UTC) (envelope-from mav@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u6A19GmA090927; Sun, 10 Jul 2016 01:09:16 GMT (envelope-from mav@FreeBSD.org) Received: (from mav@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u6A19Gef090926; Sun, 10 Jul 2016 01:09:16 GMT (envelope-from mav@FreeBSD.org) Message-Id: <201607100109.u6A19Gef090926@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: mav set sender to mav@FreeBSD.org using -f From: Alexander Motin Date: Sun, 10 Jul 2016 01:09:16 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r302510 - head/sys/dev/ntb/ntb_hw X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 10 Jul 2016 01:09:18 -0000 Author: mav Date: Sun Jul 10 01:09:16 2016 New Revision: 302510 URL: https://svnweb.freebsd.org/changeset/base/302510 Log: Simplify MSIX MW BAR xlat setup, and don't forget to unlock its limit. The last fixes SB01BASE_LOCKUP workaround after driver reload. Modified: head/sys/dev/ntb/ntb_hw/ntb_hw.c Modified: head/sys/dev/ntb/ntb_hw/ntb_hw.c ============================================================================== --- head/sys/dev/ntb/ntb_hw/ntb_hw.c Sun Jul 10 00:08:40 2016 (r302509) +++ head/sys/dev/ntb/ntb_hw/ntb_hw.c Sun Jul 10 01:09:16 2016 (r302510) @@ -1817,42 +1817,23 @@ xeon_setup_b2b_mw(struct ntb_softc *ntb, ntb_reg_write(8, XEON_SBAR4XLAT_OFFSET, 0); if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) { - size_t size, xlatoffset; + uint32_t xlat_reg, lmt_reg; enum ntb_bar bar_num; - bar_num = ntb_mw_to_bar(ntb, ntb->msix_mw_idx); - switch (bar_num) { - case NTB_B2B_BAR_1: - size = 8; - xlatoffset = XEON_SBAR2XLAT_OFFSET; - break; - case NTB_B2B_BAR_2: - xlatoffset = XEON_SBAR4XLAT_OFFSET; - if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) - size = 4; - else - size = 8; - break; - case NTB_B2B_BAR_3: - xlatoffset = XEON_SBAR5XLAT_OFFSET; - size = 4; - break; - default: - KASSERT(false, ("Bogus msix mw idx: %u", - ntb->msix_mw_idx)); - return (EINVAL); - } - /* * We point the chosen MSIX MW BAR xlat to remote LAPIC for * workaround */ - if (size == 4) { - ntb_reg_write(4, xlatoffset, MSI_INTEL_ADDR_BASE); - ntb->msix_xlat = ntb_reg_read(4, xlatoffset); + bar_num = ntb_mw_to_bar(ntb, ntb->msix_mw_idx); + bar_get_xlat_params(ntb, bar_num, NULL, &xlat_reg, &lmt_reg); + if (bar_is_64bit(ntb, bar_num)) { + ntb_reg_write(8, xlat_reg, MSI_INTEL_ADDR_BASE); + ntb->msix_xlat = ntb_reg_read(8, xlat_reg); + ntb_reg_write(8, lmt_reg, 0); } else { - ntb_reg_write(8, xlatoffset, MSI_INTEL_ADDR_BASE); - ntb->msix_xlat = ntb_reg_read(8, xlatoffset); + ntb_reg_write(4, xlat_reg, MSI_INTEL_ADDR_BASE); + ntb->msix_xlat = ntb_reg_read(4, xlat_reg); + ntb_reg_write(8, lmt_reg, 0); } ntb->peer_lapic_bar = &ntb->bar_info[bar_num];