From owner-svn-src-all@freebsd.org Sat Jul 4 18:16:43 2015 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 4AC139117; Sat, 4 Jul 2015 18:16:43 +0000 (UTC) (envelope-from jhibbits@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 1A2F11095; Sat, 4 Jul 2015 18:16:43 +0000 (UTC) (envelope-from jhibbits@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.70]) by repo.freebsd.org (8.14.9/8.14.9) with ESMTP id t64IGgsU046049; Sat, 4 Jul 2015 18:16:42 GMT (envelope-from jhibbits@FreeBSD.org) Received: (from jhibbits@localhost) by repo.freebsd.org (8.14.9/8.14.9/Submit) id t64IGgOE046047; Sat, 4 Jul 2015 18:16:42 GMT (envelope-from jhibbits@FreeBSD.org) Message-Id: <201507041816.t64IGgOE046047@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: jhibbits set sender to jhibbits@FreeBSD.org using -f From: Justin Hibbits Date: Sat, 4 Jul 2015 18:16:42 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r285144 - in head/sys/powerpc: include powerpc X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 04 Jul 2015 18:16:43 -0000 Author: jhibbits Date: Sat Jul 4 18:16:41 2015 New Revision: 285144 URL: https://svnweb.freebsd.org/changeset/base/285144 Log: Add machine check register printing This will print out the Memory Subsystem Status Register on MPC745x (G4+ class), and the Machine Check Status Register on Book-E class CPUs, to aid in debugging machine checks. Other relevant registers, for other CPUs, can be added in the future. Modified: head/sys/powerpc/include/spr.h head/sys/powerpc/powerpc/trap.c Modified: head/sys/powerpc/include/spr.h ============================================================================== --- head/sys/powerpc/include/spr.h Sat Jul 4 17:38:56 2015 (r285143) +++ head/sys/powerpc/include/spr.h Sat Jul 4 18:16:41 2015 (r285144) @@ -527,6 +527,14 @@ #define MSSCR0_ABD 0x00100000 /* 11: address bus driven (read-only) */ #define MSSCR0_MBZ 0x000fffff /* 12-31: must be zero */ #define MSSCR0_L2PFE 0x00000003 /* 30-31: L2 prefetch enable */ +#define SPR_MSSSR0 0x3f7 /* .6. Memory Subsystem Status Register (MPC745x) */ +#define MSSSR0_L2TAG 0x00040000 /* 13: L2 tag parity error */ +#define MSSSR0_L2DAT 0x00020000 /* 14: L2 data parity error */ +#define MSSSR0_L3TAG 0x00010000 /* 15: L3 tag parity error */ +#define MSSSR0_L3DAT 0x00008000 /* 16: L3 data parity error */ +#define MSSSR0_APE 0x00004000 /* 17: Address parity error */ +#define MSSSR0_DPE 0x00002000 /* 18: Data parity error */ +#define MSSSR0_TEA 0x00001000 /* 19: Bus transfer error acknowledge */ #define SPR_LDSTCR 0x3f8 /* .6. Load/Store Control Register */ #define SPR_L2PM 0x3f8 /* .6. L2 Private Memory Control Register */ #define SPR_L2CR 0x3f9 /* .6. L2 Control Register */ Modified: head/sys/powerpc/powerpc/trap.c ============================================================================== --- head/sys/powerpc/powerpc/trap.c Sat Jul 4 17:38:56 2015 (r285143) +++ head/sys/powerpc/powerpc/trap.c Sat Jul 4 18:16:41 2015 (r285144) @@ -400,6 +400,7 @@ trap_fatal(struct trapframe *frame) static void printtrap(u_int vector, struct trapframe *frame, int isfatal, int user) { + uint16_t ver; printf("\n"); printf("%s %s trap:\n", isfatal ? "fatal" : "handled", @@ -421,6 +422,17 @@ printtrap(u_int vector, struct trapframe case EXC_ITMISS: printf(" virtual address = 0x%" PRIxPTR "\n", frame->srr0); break; + case EXC_MCHK: + ver = mfpvr() >> 16; +#if defined(AIM) + if (MPC745X_P(ver)) + printf(" msssr0 = 0x%x\n", + mfspr(SPR_MSSSR0)); +#elif defined(BOOKE) + printf(" mcsr = 0x%x\n", + mfspr(SPR_MCSR)); +#endif + break; } #ifdef BOOKE printf(" esr = 0x%" PRIxPTR "\n",