From owner-freebsd-arch Sun Jan 20 14:52: 3 2002 Delivered-To: freebsd-arch@freebsd.org Received: from khavrinen.lcs.mit.edu (khavrinen.lcs.mit.edu [18.24.4.193]) by hub.freebsd.org (Postfix) with ESMTP id 8B76C37B419 for ; Sun, 20 Jan 2002 14:52:01 -0800 (PST) Received: (from wollman@localhost) by khavrinen.lcs.mit.edu (8.11.4/8.11.4) id g0KMpq032842; Sun, 20 Jan 2002 17:51:52 -0500 (EST) (envelope-from wollman) Date: Sun, 20 Jan 2002 17:51:52 -0500 (EST) From: Garrett Wollman Message-Id: <200201202251.g0KMpq032842@khavrinen.lcs.mit.edu> To: Peter Jeremy Cc: arch@FreeBSD.ORG Subject: Re: 64 bit counters again In-Reply-To: <20020121082826.Z72285@gsmx07.alcatel.com.au> References: <200201190350.g0J3oNN08944@khavrinen.lcs.mit.edu> <3C48FCEF.9190CA08@mindspring.com> <20020121082826.Z72285@gsmx07.alcatel.com.au> Sender: owner-freebsd-arch@FreeBSD.ORG Precedence: bulk List-ID: List-Archive: (Web Archive) List-Help: (List Instructions) List-Subscribe: List-Unsubscribe: X-Loop: FreeBSD.ORG < said: > 64-bit equivalents to the above IA32 instruction are: > IA32: > movl mem,%eax > movl 4+mem,%edx > 1: movl reg_lo,%ebx > movl reg_hi,%ecx > addl %eax,%ebx > adcl %edx,%ecx > lock cmpxchg8b mem > jnz 1b Actually, that local label needs to be two instructions earlier. The beauty of this instruction sequence is that it is also atomic with respect to interrupts on the local processor. > I don't know SPARCv9 or IA64, so can't comment on those, but from > Garrett's comments, the IA64 code is similar to the IA32 code and > the SPARCv9 code is similar to the Alpha code. Actually, the SPARC would be similar to the Intel. I think only Alpha and MIPS implemented the LL/SC version of this primitive. -GAWollman To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-arch" in the body of the message