From owner-svn-src-head@freebsd.org Mon May 7 07:26:49 2018 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 49D3AFA8FC4; Mon, 7 May 2018 07:26:49 +0000 (UTC) (envelope-from manu@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id ED5B97B099; Mon, 7 May 2018 07:26:48 +0000 (UTC) (envelope-from manu@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id CFE3218300; Mon, 7 May 2018 07:26:48 +0000 (UTC) (envelope-from manu@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w477Qmkn071631; Mon, 7 May 2018 07:26:48 GMT (envelope-from manu@FreeBSD.org) Received: (from manu@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w477QmJE071630; Mon, 7 May 2018 07:26:48 GMT (envelope-from manu@FreeBSD.org) Message-Id: <201805070726.w477QmJE071630@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: manu set sender to manu@FreeBSD.org using -f From: Emmanuel Vadot Date: Mon, 7 May 2018 07:26:48 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r333314 - head/sys/arm64/rockchip/clk X-SVN-Group: head X-SVN-Commit-Author: manu X-SVN-Commit-Paths: head/sys/arm64/rockchip/clk X-SVN-Commit-Revision: 333314 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.25 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 07 May 2018 07:26:49 -0000 Author: manu Date: Mon May 7 07:26:48 2018 New Revision: 333314 URL: https://svnweb.freebsd.org/changeset/base/333314 Log: arm64: rockchip: rk3328: Add armclk clock Add the clock definition for the arm clock. While here remove the indexes in the clock table as we will need clock with a 0 index (non-exported clocks). Modified: head/sys/arm64/rockchip/clk/rk3328_cru.c Modified: head/sys/arm64/rockchip/clk/rk3328_cru.c ============================================================================== --- head/sys/arm64/rockchip/clk/rk3328_cru.c Mon May 7 07:02:26 2018 (r333313) +++ head/sys/arm64/rockchip/clk/rk3328_cru.c Mon May 7 07:26:48 2018 (r333314) @@ -191,6 +191,25 @@ static struct rk_clk_composite_def aclk_bus_pre = { .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; +#define ARMCLK 6 +static const char *armclk_parents[] = {"apll", "gpll", "dpll", "npll" }; +static struct rk_clk_composite_def armclk = { + .clkdef = { + .id = ARMCLK, + .name = "armclk", + .parent_names = armclk_parents, + .parent_cnt = nitems(armclk_parents), + }, + .muxdiv_offset = 0x100, + .mux_shift = 6, + .mux_width = 2, + + .div_shift = 0, + .div_width = 5, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX, +}; + /* CRU_CLKSEL_CON1 */ #define PCLK_BUS_PRE 216 @@ -377,61 +396,65 @@ static struct rk_clk_composite_def emmc = { }; static struct rk_clk rk3328_clks[] = { - [PLL_APLL] = { + { .type = RK_CLK_PLL, .clk.pll = &apll }, - [PLL_DPLL] = { + { .type = RK_CLK_PLL, .clk.pll = &dpll }, - [PLL_CPLL] = { + { .type = RK_CLK_PLL, .clk.pll = &cpll }, - [PLL_GPLL] = { + { .type = RK_CLK_PLL, .clk.pll = &gpll }, - [PLL_NPLL] = { + { .type = RK_CLK_PLL, .clk.pll = &npll }, - [ACLK_BUS_PRE] = { + { .type = RK_CLK_COMPOSITE, .clk.composite = &aclk_bus_pre }, - [HCLK_BUS_PRE] = { + { .type = RK_CLK_COMPOSITE, + .clk.composite = &armclk + }, + { + .type = RK_CLK_COMPOSITE, .clk.composite = &hclk_bus_pre }, - [PCLK_BUS_PRE] = { + { .type = RK_CLK_COMPOSITE, .clk.composite = &pclk_bus_pre }, - [ACLK_PERI_PRE] = { + { .type = RK_CLK_COMPOSITE, .clk.composite = &aclk_peri_pre, }, - [PCLK_PERI] = { + { .type = RK_CLK_COMPOSITE, .clk.composite = &pclk_peri, }, - [HCLK_PERI] = { + { .type = RK_CLK_COMPOSITE, .clk.composite = &hclk_peri, }, - [SCLK_SDMMC] = { + { .type = RK_CLK_COMPOSITE, .clk.composite = &sdmmc }, - [SCLK_SDIO] = { + { .type = RK_CLK_COMPOSITE, .clk.composite = &sdio }, - [SCLK_EMMC] = { + { .type = RK_CLK_COMPOSITE, .clk.composite = &emmc },