From owner-svn-src-head@freebsd.org Tue Nov 29 04:32:16 2016 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 170A2C5B163; Tue, 29 Nov 2016 04:32:16 +0000 (UTC) (envelope-from jchandra@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id D3EF019DA; Tue, 29 Nov 2016 04:32:15 +0000 (UTC) (envelope-from jchandra@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id uAT4WFbv050561; Tue, 29 Nov 2016 04:32:15 GMT (envelope-from jchandra@FreeBSD.org) Received: (from jchandra@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id uAT4WF8c050560; Tue, 29 Nov 2016 04:32:15 GMT (envelope-from jchandra@FreeBSD.org) Message-Id: <201611290432.uAT4WF8c050560@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: jchandra set sender to jchandra@FreeBSD.org using -f From: "Jayachandran C." Date: Tue, 29 Nov 2016 04:32:15 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r309276 - head/sys/dev/uart X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Nov 2016 04:32:16 -0000 Author: jchandra Date: Tue Nov 29 04:32:14 2016 New Revision: 309276 URL: https://svnweb.freebsd.org/changeset/base/309276 Log: Fix interrupt clear in pl011 uart receive function Clear the interrupt state before reading the input char from the input FIFO. In the current code there is a window between the read to the data register and the write to the the ICR, during which an input char will not cause an interrupt. This fixes the issue by which the serial port input on QEMU freezes when using the emulated pl011 serial port. Modified: head/sys/dev/uart/uart_dev_pl011.c Modified: head/sys/dev/uart/uart_dev_pl011.c ============================================================================== --- head/sys/dev/uart/uart_dev_pl011.c Tue Nov 29 01:08:09 2016 (r309275) +++ head/sys/dev/uart/uart_dev_pl011.c Tue Nov 29 04:32:14 2016 (r309276) @@ -443,6 +443,8 @@ uart_pl011_bus_receive(struct uart_softc sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; break; } + + __uart_setreg(bas, UART_ICR, (UART_RXREADY | RIS_RTIM)); xc = __uart_getreg(bas, UART_DR); rx = xc & 0xff; @@ -451,8 +453,6 @@ uart_pl011_bus_receive(struct uart_softc if (xc & DR_PE) rx |= UART_STAT_PARERR; - __uart_setreg(bas, UART_ICR, (UART_RXREADY | RIS_RTIM)); - uart_rx_put(sc, rx); ints = __uart_getreg(bas, UART_MIS); }