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From: Jung-uk Kim <jkim@FreeBSD.org>
Date: Wed, 22 Jun 2011 16:40:45 +0000 (UTC)
To: cvs-src-old@freebsd.org
X-FreeBSD-CVS-Branch: HEAD
Subject: cvs commit: src/sys/dev/acpica acpi_cpu.c src/sys/kern
 kern_clocksource.c src/sys/sys systm.h src/sys/x86/x86 tsc.c
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jkim        2011-06-22 16:40:45 UTC

  FreeBSD src repository

  Modified files:
    sys/dev/acpica       acpi_cpu.c 
    sys/kern             kern_clocksource.c 
    sys/sys              systm.h 
    sys/x86/x86          tsc.c 
  Log:
  SVN rev 223426 on 2011-06-22 16:40:45Z by jkim
  
  Set negative quality to TSC timecounter when C3 state is enabled for Intel
  processors unless the invariant TSC bit of CPUID is set.  Intel processors
  may stop incrementing TSC when DPSLP# pin is asserted, according to Intel
  processor manuals, i. e., TSC timecounter is useless if the processor can
  enter deep sleep state (C3/C4).  This problem was accidentally uncovered by
  r222869, which increased timecounter quality of P-state invariant TSC, e.g.,
  for Core2 Duo T5870 (Family 6, Model f) and Atom N270 (Family 6, Model 1c).
  
  Reported by:    Fabian Keil (freebsd-listen at fabiankeil dot de)
                  Ian FREISLICH (ianf at clue dot co dot za)
  Tested by:      Fabian Keil (freebsd-listen at fabiankeil dot de)
                  - Core2 Duo T5870 (C3 state available/enabled)
                  jkim - Xeon X5150 (C3 state unavailable)
  
  Revision  Changes    Path
  1.97      +2 -0      src/sys/dev/acpica/acpi_cpu.c
  1.17      +1 -0      src/sys/kern/kern_clocksource.c
  1.297     +1 -0      src/sys/sys/systm.h
  1.25      +13 -0     src/sys/x86/x86/tsc.c