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From: Emanuel Haupt <ehaupt@FreeBSD.org>
Date: Thu, 27 Feb 2014 13:43:28 +0000 (UTC)
To: ports-committers@freebsd.org, svn-ports-all@freebsd.org,
 svn-ports-head@freebsd.org
Subject: svn commit: r346330 - head/cad/gplcver
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Author: ehaupt
Date: Thu Feb 27 13:43:27 2014
New Revision: 346330
URL: http://svnweb.freebsd.org/changeset/ports/346330
QAT: https://qat.redports.org/buildarchive/r346330/

Log:
  Support staging

Modified:
  head/cad/gplcver/Makefile

Modified: head/cad/gplcver/Makefile
==============================================================================
--- head/cad/gplcver/Makefile	Thu Feb 27 13:38:07 2014	(r346329)
+++ head/cad/gplcver/Makefile	Thu Feb 27 13:43:27 2014	(r346330)
@@ -10,17 +10,15 @@ DISTNAME=	${PORTNAME}-${PORTVERSION:R}${
 MAINTAINER=	ports@FreeBSD.org
 COMMENT=	A Verilog HDL simulator
 
+USES=		gmake
 USE_BZIP2=	yes
+
 BUILD_WRKSRC=	${WRKSRC}/src
-USE_GMAKE=	yes
 MAKEFILE=	makefile.freebsd
 
 PLIST_FILES=	bin/cver
 
-NO_STAGE=	yes
-.include <bsd.port.pre.mk>
-
 do-install:
-	${INSTALL_PROGRAM} ${WRKSRC}/bin/cver ${PREFIX}/bin
+	${INSTALL_PROGRAM} ${WRKSRC}/bin/cver ${STAGEDIR}${PREFIX}/bin
 
-.include <bsd.port.post.mk>
+.include <bsd.port.mk>