Date: Fri, 13 Dec 1996 23:40:27 -0800 From: Erich Boleyn <erich@uruk.org> To: Peter Wemm <peter@spinner.dialix.com> Cc: smp@freebsd.org Subject: TLB shootdown problems? (was -> Re: Tried SMP kernel from early morning CVS tree ) Message-ID: <E0vYohv-0003dK-00@uruk.org> In-Reply-To: Your message of "Sat, 14 Dec 1996 09:45:16 %2B0800." <199612140145.JAA13805@spinner.DIALix.COM>
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Peter Wemm <peter@spinner.DIALix.COM> writes: > There were some good details posted on this problem a few days ago > from the other person with the P6 system, there is probably a good > clue in there. My initial reaction to the details was that it > almost looked like both cpu's accessed a shared data structure at > nearly the same time, which should be impossible due to the locking. > I can't imagine why this might be happening yet, but I must re-examine > that part of the code. An extra local tlb flush might help, but > I'm not 100% sure yet. Here's a question (I'm going to look this up myself, but thought it'd be worthwhile to see if you'd shed light on it before I get to it on my copious spare time ;-) ... How exactly are TLB shootdown IPIs implemented? (or are they any different from any other IPIs?) >From what I could see, it looks like the IPI is considered "finished" (and the function returns) when the APIC status is "delivered". This could be a problem, because the interrupt doesn't necessarily happen on the other CPU at that point (and it certainly isn't completed at that point). You really need some other mechanism to tell you that the operation has completed before you can continue. This might not be as major a problem on the P5 for implementation and shorter pipeline reasons, and the P6 also has deeper pipelines and is much faster relative to the external bus clock (which the APICs use). -- Erich Stefan Boleyn \_ E-mail (preferred): <erich@uruk.org> Mad Genius wanna-be, CyberMuffin \__ (finger me for other stats) Web: http://www.uruk.org/~erich/ Motto: "I'll live forever or die trying"
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