From owner-svn-src-head@FreeBSD.ORG Mon Nov 19 23:42:47 2012 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 2331E595; Mon, 19 Nov 2012 23:42:47 +0000 (UTC) (envelope-from adrian@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) by mx1.freebsd.org (Postfix) with ESMTP id 094278FC17; Mon, 19 Nov 2012 23:42:47 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.5/8.14.5) with ESMTP id qAJNgkR9067140; Mon, 19 Nov 2012 23:42:46 GMT (envelope-from adrian@svn.freebsd.org) Received: (from adrian@localhost) by svn.freebsd.org (8.14.5/8.14.5/Submit) id qAJNgkgl067133; Mon, 19 Nov 2012 23:42:46 GMT (envelope-from adrian@svn.freebsd.org) Message-Id: <201211192342.qAJNgkgl067133@svn.freebsd.org> From: Adrian Chadd Date: Mon, 19 Nov 2012 23:42:46 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r243317 - head/sys/dev/ath/ath_hal/ar5210 X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 19 Nov 2012 23:42:47 -0000 Author: adrian Date: Mon Nov 19 23:42:46 2012 New Revision: 243317 URL: http://svnweb.freebsd.org/changeset/base/243317 Log: Disable WEP hardware encryption on the AR5210, in order to allow other encryption types. The AR5210 only has four WEP key slots, in contrast to what the later MACs have (ie, the keycache.) So there's no way to store a "clear" key. Even if the driver is taught to not allocate CLR key entries for the AR5210, the hardware will actually attempt to decode the encrypted frames with the (likely all 0!) WEP keys. So for now, disable the hardware encryption entirely and just so it all in software. That allows both WEP -and- WPA to actually work. If someone wishes to try and make hardware WEP _but_ software WPA work, they'll have to create a HAL capability to enable/disable hardware encryption based on the current STA/Hostap mode. However, making multi-vap work with one WEP and one WPA VAP will require hardware encryption to be disabled anyway. Modified: head/sys/dev/ath/ath_hal/ar5210/ar5210.h head/sys/dev/ath/ath_hal/ar5210/ar5210_misc.c head/sys/dev/ath/ath_hal/ar5210/ar5210_recv.c head/sys/dev/ath/ath_hal/ar5210/ar5210_reset.c head/sys/dev/ath/ath_hal/ar5210/ar5210reg.h Modified: head/sys/dev/ath/ath_hal/ar5210/ar5210.h ============================================================================== --- head/sys/dev/ath/ath_hal/ar5210/ar5210.h Mon Nov 19 23:07:38 2012 (r243316) +++ head/sys/dev/ath/ath_hal/ar5210/ar5210.h Mon Nov 19 23:42:46 2012 (r243317) @@ -261,6 +261,7 @@ extern HAL_BOOL ar5210GetMibCycleCounts( HAL_SURVEY_SAMPLE *); extern void ar5210EnableDfs(struct ath_hal *, HAL_PHYERR_PARAM *); extern void ar5210GetDfsThresh(struct ath_hal *, HAL_PHYERR_PARAM *); +extern void ar5210UpdateDiagReg(struct ath_hal *ah, uint32_t val); extern u_int ar5210GetKeyCacheSize(struct ath_hal *); extern HAL_BOOL ar5210IsKeyCacheEntryValid(struct ath_hal *, uint16_t); Modified: head/sys/dev/ath/ath_hal/ar5210/ar5210_misc.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5210/ar5210_misc.c Mon Nov 19 23:07:38 2012 (r243316) +++ head/sys/dev/ath/ath_hal/ar5210/ar5210_misc.c Mon Nov 19 23:42:46 2012 (r243317) @@ -576,8 +576,6 @@ ar5210MibEvent(struct ath_hal *ah, const { } -#define AR_DIAG_SW_DIS_CRYPTO (AR_DIAG_SW_DIS_ENC | AR_DIAG_SW_DIS_DEC) - HAL_STATUS ar5210GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, uint32_t capability, uint32_t *result) @@ -585,7 +583,11 @@ ar5210GetCapability(struct ath_hal *ah, switch (type) { case HAL_CAP_CIPHER: /* cipher handled in hardware */ +#if 0 return (capability == HAL_CIPHER_WEP ? HAL_OK : HAL_ENOTSUPP); +#else + return HAL_ENOTSUPP; +#endif default: return ath_hal_getcapability(ah, type, capability, result); } @@ -608,7 +610,7 @@ ar5210SetCapability(struct ath_hal *ah, #else AH_PRIVATE(ah)->ah_diagreg = setting & 0x6; /* ACK+CTS */ #endif - OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg); + ar5210UpdateDiagReg(ah, AH_PRIVATE(ah)->ah_diagreg); return AH_TRUE; case HAL_CAP_RXORN_FATAL: /* HAL_INT_RXORN treated as fatal */ return AH_FALSE; /* NB: disallow */ @@ -677,3 +679,18 @@ void ar5210GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe) { } + +/* + * Update the diagnostic register. + * + * This merges in the diagnostic register setting with the default + * value, which may or may not involve disabling hardware encryption. + */ +void +ar5210UpdateDiagReg(struct ath_hal *ah, uint32_t val) +{ + + /* Disable all hardware encryption */ + val |= AR_DIAG_SW_DIS_CRYPTO; + OS_REG_WRITE(ah, AR_DIAG_SW, val); +} Modified: head/sys/dev/ath/ath_hal/ar5210/ar5210_recv.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5210/ar5210_recv.c Mon Nov 19 23:07:38 2012 (r243316) +++ head/sys/dev/ath/ath_hal/ar5210/ar5210_recv.c Mon Nov 19 23:42:46 2012 (r243317) @@ -86,7 +86,7 @@ ar5210StopDmaReceive(struct ath_hal *ah) void ar5210StartPcuReceive(struct ath_hal *ah) { - OS_REG_WRITE(ah, AR_DIAG_SW, + ar5210UpdateDiagReg(ah, OS_REG_READ(ah, AR_DIAG_SW) & ~(AR_DIAG_SW_DIS_RX)); } @@ -96,7 +96,7 @@ ar5210StartPcuReceive(struct ath_hal *ah void ar5210StopPcuReceive(struct ath_hal *ah) { - OS_REG_WRITE(ah, AR_DIAG_SW, + ar5210UpdateDiagReg(ah, OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_SW_DIS_RX); } Modified: head/sys/dev/ath/ath_hal/ar5210/ar5210_reset.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5210/ar5210_reset.c Mon Nov 19 23:07:38 2012 (r243316) +++ head/sys/dev/ath/ath_hal/ar5210/ar5210_reset.c Mon Nov 19 23:42:46 2012 (r243317) @@ -190,7 +190,7 @@ ar5210Reset(struct ath_hal *ah, HAL_OPMO OS_REG_WRITE(ah, AR_CLR_TMASK, 1); OS_REG_WRITE(ah, AR_TRIG_LEV, 1); /* minimum */ - OS_REG_WRITE(ah, AR_DIAG_SW, 0); + ar5210UpdateDiagReg(ah, 0); OS_REG_WRITE(ah, AR_CFP_PERIOD, 0); OS_REG_WRITE(ah, AR_TIMER0, 0); /* next beacon time */ @@ -285,7 +285,7 @@ ar5210Reset(struct ath_hal *ah, HAL_OPMO if (ahp->ah_ctstimeout != (u_int) -1) ar5210SetCTSTimeout(ah, ahp->ah_ctstimeout); if (AH_PRIVATE(ah)->ah_diagreg != 0) - OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg); + ar5210UpdateDiagReg(ah, AH_PRIVATE(ah)->ah_diagreg); AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */ @@ -454,7 +454,7 @@ ar5210PerCalibrationN(struct ath_hal *ah if (ichan == AH_NULL) return AH_FALSE; /* Disable tx and rx */ - OS_REG_WRITE(ah, AR_DIAG_SW, + ar5210UpdateDiagReg(ah, OS_REG_READ(ah, AR_DIAG_SW) | (AR_DIAG_SW_DIS_TX | AR_DIAG_SW_DIS_RX)); /* Disable Beacon Enable */ @@ -551,7 +551,7 @@ ar5210PerCalibrationN(struct ath_hal *ah } /* Clear tx and rx disable bit */ - OS_REG_WRITE(ah, AR_DIAG_SW, + ar5210UpdateDiagReg(ah, OS_REG_READ(ah, AR_DIAG_SW) & ~(AR_DIAG_SW_DIS_TX | AR_DIAG_SW_DIS_RX)); /* Re-enable Beacons */ Modified: head/sys/dev/ath/ath_hal/ar5210/ar5210reg.h ============================================================================== --- head/sys/dev/ath/ath_hal/ar5210/ar5210reg.h Mon Nov 19 23:07:38 2012 (r243316) +++ head/sys/dev/ath/ath_hal/ar5210/ar5210reg.h Mon Nov 19 23:42:46 2012 (r243317) @@ -385,6 +385,7 @@ #define AR_DIAG_SW_SCVRAM_SEED 0x0003f800 /* fixed scrambler seed */ #define AR_DIAG_SW_DIS_SEQ_INC 0x00040000 /* seq increment disable */ #define AR_DIAG_SW_FRAME_NV0 0x00080000 /* accept frame vers != 0 */ +#define AR_DIAG_SW_DIS_CRYPTO (AR_DIAG_SW_DIS_ENC | AR_DIAG_SW_DIS_DEC) #define AR_DIAG_SW_BITS \ "\20\1DIS_WEP_ACK\2DIS_ACK\3DIS_CTS\4DIS_ENC\5DIS_DEC\6DIS_TX"\ "\7DIS_RX\10LOOP_BACK\11CORR_FCS\12CHAN_INFO\13EN_SCRAM_SEED"\