From owner-freebsd-arm@FreeBSD.ORG Sat Dec 15 20:21:11 2012 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id E0B74A15 for ; Sat, 15 Dec 2012 20:21:11 +0000 (UTC) (envelope-from freebsd@damnhippie.dyndns.org) Received: from duck.symmetricom.us (duck.symmetricom.us [206.168.13.214]) by mx1.freebsd.org (Postfix) with ESMTP id A79438FC0A for ; Sat, 15 Dec 2012 20:21:10 +0000 (UTC) Received: from damnhippie.dyndns.org (daffy.symmetricom.us [206.168.13.218]) by duck.symmetricom.us (8.14.5/8.14.5) with ESMTP id qBFKL9jl059530 for ; Sat, 15 Dec 2012 13:21:10 -0700 (MST) (envelope-from freebsd@damnhippie.dyndns.org) Received: from [172.22.42.240] (revolution.hippie.lan [172.22.42.240]) by damnhippie.dyndns.org (8.14.3/8.14.3) with ESMTP id qBFKKldt060620 for ; Sat, 15 Dec 2012 13:20:47 -0700 (MST) (envelope-from freebsd@damnhippie.dyndns.org) Subject: arm cache fixes From: Ian Lepore To: freebsd-arm@freebsd.org Content-Type: text/plain; charset="us-ascii" Date: Sat, 15 Dec 2012 13:20:47 -0700 Message-ID: <1355602847.1198.83.camel@revolution.hippie.lan> Mime-Version: 1.0 X-Mailer: Evolution 2.32.1 FreeBSD GNOME Team Port Content-Transfer-Encoding: 7bit X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 15 Dec 2012 20:21:11 -0000 Yes, I've submitted yet another patch for an arm cache maintenance bug. Just to be clear: it is NOT the fix for the arm v6/v7 writeback problem. It also doesn't apply to Marvell/Sheeva-based armv5 systems, because they have their own SoC-specific cache maintenance routines. It does apply to most other armv4 and v5 systems. Speaking of the armv6/v7 bug that happens with writeback enabled... I took a hard look at the low-level asm code for those, and nothing jumps out at me as wrong. But then, I've looked at the armv4 low level routines many times before, starting in 2009 when I first started fighting cache coherency problems, and I never noticed those incorrect 'bpl' instructions before. (I've been doing arm asm since 1993, and I'm still always tripped up by the branch mnemonics used with arm.) I've been calling it "the armv6/v7" problem, but do we know whether it's both of those architectures, or if it's v7-only? There's a huge difference between the cache maintenance schemes for the two. If it happens on both, we should probably focus on the busdma_machdep code. If it's v7 only, maybe it's low-level code (which looks reasonable on its face, but I need to study the ARM ARM for v7 stuff more). -- Ian