Date: Sun, 30 Nov 1997 20:03:35 GMT From: jak@cetlink.net (John Kelly) To: John-Mark Gurney <gurney_j@resnet.uoregon.edu> Cc: Bruce Evans <bde@zeta.org.au>, hackers@freebsd.org Subject: Re: 650 UART, SIO driver, 8259 PIC Message-ID: <3484c18f.19943322@mail.cetlink.net> In-Reply-To: <19971130030719.29570@hydrogen.nike.efn.org> References: <199711301019.VAA09201@godzilla.zeta.org.au> <19971130030719.29570@hydrogen.nike.efn.org>
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On Sun, 30 Nov 1997 03:07:19 -0800, John-Mark Gurney <gurney_j@efn.org> wrote: >ok, I see what you mean.. :) that's good news, but it still doesn't >force that the ports be in proper order... we'll just have to document >it this way if they want their AST/4 port board working.. just hope that >people won't complain because they didn't have their setup correct in >the first place.. In the section discussing IRQ control and status registers, the man page only mentions four ports per interrupt sharing "group." It also says that "control and status registers for a group, if any, must be mapped to the scratch register (register 7) of a port in the group. Such a port is called a master port." With only eight bits in the scratch register, mapping both a control and status register to it will limit your interrupt sharing group to a maximum of four ports. A software design based on that hardware configuration seems too restrictive. Eight port boards which share a single IRQ are common now. The board I have does not even use the idea of mapping. You simply jumper it to select an unused I/O address where the status port will appear. It renders obsolete the idea of a "master" port. John
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