Date: Thu, 15 Oct 2020 22:11:24 +0000 (UTC) From: Yuri Victorovich <yuri@FreeBSD.org> To: ports-committers@freebsd.org, svn-ports-all@freebsd.org, svn-ports-head@freebsd.org Subject: svn commit: r552483 - head/cad/verilator Message-ID: <202010152211.09FMBOMu083745@repo.freebsd.org>
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Author: yuri Date: Thu Oct 15 22:11:24 2020 New Revision: 552483 URL: https://svnweb.freebsd.org/changeset/ports/552483 Log: cad/verilator: Update 4.100 -> 4.102 Modified: head/cad/verilator/Makefile head/cad/verilator/distinfo Modified: head/cad/verilator/Makefile ============================================================================== --- head/cad/verilator/Makefile Thu Oct 15 21:54:40 2020 (r552482) +++ head/cad/verilator/Makefile Thu Oct 15 22:11:24 2020 (r552483) @@ -1,13 +1,9 @@ # $FreeBSD$ PORTNAME= verilator -DISTVERSION= 4.100 -PORTREVISION= 1 +DISTVERSION= 4.102 CATEGORIES= cad MASTER_SITES= https://www.veripool.org/ftp/ - -PATCH_SITES= https://github.com/${PORTNAME}/${PORTNAME}/commit/ -PATCHFILES= d750a54e90df1161cfe9502ca56f298005283372.diff:-p1 # make->gmake patch MAINTAINER= yuri@FreeBSD.org COMMENT= Synthesizable Verilog to C++ compiler Modified: head/cad/verilator/distinfo ============================================================================== --- head/cad/verilator/distinfo Thu Oct 15 21:54:40 2020 (r552482) +++ head/cad/verilator/distinfo Thu Oct 15 22:11:24 2020 (r552483) @@ -1,5 +1,3 @@ -TIMESTAMP = 1600224270 -SHA256 (verilator-4.100.tgz) = 22db8132209849bc09f567c48fe1eebea272102aa7b8eb1e39df520cc37ce16d -SIZE (verilator-4.100.tgz) = 2747140 -SHA256 (d750a54e90df1161cfe9502ca56f298005283372.diff) = 27454dbaa502d0cd2e815416e659062a408a760d48604e18d8401499cebfa1de -SIZE (d750a54e90df1161cfe9502ca56f298005283372.diff) = 500 +TIMESTAMP = 1602797123 +SHA256 (verilator-4.102.tgz) = 7c74f2ac4a0e8c1dbcbcf06e998dc8a389bb29469d7f491588470b859a0b8d5d +SIZE (verilator-4.102.tgz) = 2767422
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