Date: Sat, 19 Oct 2019 22:07:56 +0000 (UTC) From: Yuri Victorovich <yuri@FreeBSD.org> To: ports-committers@freebsd.org, svn-ports-all@freebsd.org, svn-ports-head@freebsd.org Subject: svn commit: r514852 - head/cad/verilator Message-ID: <201910192207.x9JM7u0d090027@repo.freebsd.org>
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Author: yuri Date: Sat Oct 19 22:07:56 2019 New Revision: 514852 URL: https://svnweb.freebsd.org/changeset/ports/514852 Log: cad/verilator: Update 4.008 -> 4.020 PR: 241346 Approved by: kevinz5000@gmail.com (maintainer) Modified: head/cad/verilator/Makefile head/cad/verilator/distinfo head/cad/verilator/pkg-plist Modified: head/cad/verilator/Makefile ============================================================================== --- head/cad/verilator/Makefile Sat Oct 19 21:59:51 2019 (r514851) +++ head/cad/verilator/Makefile Sat Oct 19 22:07:56 2019 (r514852) @@ -1,8 +1,7 @@ # $FreeBSD$ PORTNAME= verilator -PORTVERSION= 4.008 -PORTREVISION= 2 +DISTVERSION= 4.020 CATEGORIES= cad MASTER_SITES= https://www.veripool.org/ftp/ @@ -10,9 +9,9 @@ MAINTAINER= kevinz5000@gmail.com COMMENT= Synthesizable Verilog to C++ compiler LICENSE= GPLv3 -LICENSE_FILE= ${WRKSRC}/COPYING +LICENSE_FILE= ${WRKSRC}/LICENSE -USES= bison compiler:c++11-lang gmake pathfix perl5 tar:tgz +USES= bison compiler:c++14-lang gmake pathfix perl5 tar:tgz GNU_CONFIGURE= yes CONFIGURE_ENV= INSTALL_PROGRAM="${INSTALL_SCRIPT}" @@ -25,6 +24,6 @@ post-build: @${STRIP_CMD} ${WRKSRC}/bin/verilator_bin post-install: - ${RM} ${STAGEDIR}${PREFIX}/bin/verilator_bin_dbg ${STAGEDIR}${PREFIX}/bin/verilator_coverage_bin_dbg + @${RM} ${STAGEDIR}${PREFIX}/bin/verilator_bin_dbg ${STAGEDIR}${PREFIX}/bin/verilator_coverage_bin_dbg .include <bsd.port.mk> Modified: head/cad/verilator/distinfo ============================================================================== --- head/cad/verilator/distinfo Sat Oct 19 21:59:51 2019 (r514851) +++ head/cad/verilator/distinfo Sat Oct 19 22:07:56 2019 (r514852) @@ -1,3 +1,3 @@ -TIMESTAMP = 1548558502 -SHA256 (verilator-4.008.tgz) = d5cef6edd3bdb7754776d902daae7a7e5dd662baa7c7f895cb7028b1d6910cac -SIZE (verilator-4.008.tgz) = 2519234 +TIMESTAMP = 1571513048 +SHA256 (verilator-4.020.tgz) = abd79fc2a54cab9da33dfccd669bda3baa71e79060abec17517f0b7374dbc31a +SIZE (verilator-4.020.tgz) = 2355177 Modified: head/cad/verilator/pkg-plist ============================================================================== --- head/cad/verilator/pkg-plist Sat Oct 19 21:59:51 2019 (r514851) +++ head/cad/verilator/pkg-plist Sat Oct 19 22:07:56 2019 (r514852) @@ -32,8 +32,6 @@ man/man1/verilator_profcfunc.1.gz %%DATADIR%%/include/gtkwave/fst_config.h %%DATADIR%%/include/gtkwave/fstapi.c %%DATADIR%%/include/gtkwave/fstapi.h -%%DATADIR%%/include/gtkwave/lxt2_write.cpp -%%DATADIR%%/include/gtkwave/lxt2_write.h %%DATADIR%%/include/gtkwave/lz4.c %%DATADIR%%/include/gtkwave/lz4.h %%DATADIR%%/include/gtkwave/wavealloca.h @@ -52,8 +50,6 @@ man/man1/verilator_profcfunc.1.gz %%DATADIR%%/include/verilated_fst_c.h %%DATADIR%%/include/verilated_heavy.h %%DATADIR%%/include/verilated_imp.h -%%DATADIR%%/include/verilated_lxt2_c.cpp -%%DATADIR%%/include/verilated_lxt2_c.h %%DATADIR%%/include/verilated_save.cpp %%DATADIR%%/include/verilated_save.h %%DATADIR%%/include/verilated_sc.h
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