Date: Tue, 9 May 2006 10:47:08 +0200 From: Alexander Leidinger <Alexander@Leidinger.net> To: Ivan Voras <ivoras@fer.hr> Cc: current@freebsd.org Subject: Re: I_686 MMX / 3DNOW / SSE / SSE2 ? Message-ID: <20060509104708.65c1b651@Magellan.Leidinger.net> In-Reply-To: <445F7814.90905@fer.hr> References: <61809.192.168.1.21.1147030254.squirrel@192.168.1.21> <86d5epp5tv.fsf@xps.des.no> <20060508132721.36915d94@Magellan.Leidinger.net> <445F7814.90905@fer.hr>
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Quoting Ivan Voras <ivoras@fer.hr> (Mon, 08 May 2006 18:55:48 +0200): > Alexander Leidinger wrote: > > > The patches which port the revamped FPU handling from DFly don't have > > this expensive behavior for every switch. AFAIR only when the kernel > > used the FPU some context is saved. It also allows to use SIMD > > instructions in the kernel (this may be beneficial in some places). > > For what it's worth - it would be interesting to see if XOR calculations > in GRAID3 or VINUM can be speeded up by using SSE (I think SSE3 is > needed for 128 bit integer ops?) AFAIR icc did some vector optimizations in the vinum code at the time when I worked on getting the kernel "icc-clean", but since we can't use SIMD in the kernel, I don't know if it is beneficial or not. Here's the mail about the ported FPU handling, in case someone wants to play with it: http://lists.freebsd.org/pipermail/freebsd-arch/2006-March/004932.html Bye, Alexander. -- Press every key to continue. http://www.Leidinger.net Alexander @ Leidinger.net GPG fingerprint = C518 BC70 E67F 143F BE91 3365 79E2 9C60 B006 3FE7 WL http://www.amazon.de/exec/obidos/registry/1FZ4DTHQE9PQ8/ref=wl_em_to/
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