Date: Wed, 26 Nov 1997 16:15:30 GMT From: mouth@ibm.net (John Kelly) To: Bruce Evans <bde@zeta.org.au> Cc: hackers@FreeBSD.ORG Subject: 650 UART, SIO driver, 8259 PIC Message-ID: <347c331c.3815914@smtp-gw01.ny.us.ibm.net> In-Reply-To: <199711250910.UAA29294@godzilla.zeta.org.au> References: <199711250910.UAA29294@godzilla.zeta.org.au>
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On Tue, 25 Nov 1997 20:10:00 +1100, Bruce Evans <bde@zeta.org.au>
wrote:
>>The PIC which ultimately receives the electrical signal as output from
>> the OR gate has no care for falling edges, only rising ones.
>
>It does care. After an irq has been acked, the edge latch remains set
>until the irq goes low (or at least until it is low when sampled on the
>next bus clock cycle). The handler must not return with the edge latch
>set, at least for 16x50 devices, since if the edge latch is set then
>there must be a device irq and returning would give up the only chance
>of handling the irq.
I don't see the potential for that problem with FIFOed UARTs where
several have their INT output ORed on a multiport interrupt sharing
card. Perhaps with non-FIFOed UARTS.
One of my objectives is implementing input burst mode for 550 (or
better) UARTs. A second driver called sio550.c could shed the legacy
8250/16450 baggage. That's not only reasonable, it's even wise given
the prevalence of 550s and higher in the market today.
And as far as the edge latch goes, the handler apparently *can* safely
return with the edge latch set if there was a down/up transition on
the IRQ line before EOI. Although that seems unlikely because of the
relatively large time needed to refill any UART to its FIFO trigger
level after draining it once, perhaps theoretically it could happen on
a multiport card where you've acked your interrupt, drained all the
UARTs (only once, not looping for a second pass), and then receive a
new interrupt from one of the UARTs you've already drained. I gather
that is the case you are concerned about.
If you can't reach the last UART before INT is raised a second time
by a previously drained UART, then you are saturated with serial
interrupts and your machine would be overloaded to the point of doing
no useful work except servicing serial interrupts. That is the only
case where you would never have a down/up transition on the IRQ line
after clearing the INT output of the last UART, and then the issue of
a lost interrupt becomes moot anyway.
But in the non-pathological case of a machine which is able to do
other useful work, by clearing the INT output of the last UART before
any of the previously drained UARTs can raise their INT output again,
you will have at least one down/up transition on the IRQ line. If you
agree with following writer's conclusion, the handler *can* safely
issue EOI and return after making only one pass to drain the UARTs.
Attributed to Chris Hall (chris@locomotive.com)
2. The Jargon
An interrupt source, fed into an 8259A, is known as an IRQ --
Interrupt Request. An 8259A has 8 IRQ inputs.
The 8 IRQ inputs are fed into an 8 bit Interrupt Request
Register (IRR), via some "rising edge" detection logic (8 bit
Edge Sense Register -- ESR).
The 8259A can be told to mask off any of the IRQ. The 8259A
has an 8 bit Interrupt Mask Register (IMR). A one bit in the
IMR masks off the corresponding IRQ.
To perform its priority arbitration the 8259A has an 8 bit In
Service Register (ISR). In the register a bit is set to 1 when
the corresponding interrupt has been passed to the CPU, and the
CPU has not yet signalled End of Interrupt (EOI)
The CPU interrupt input is known as INTR. The 8259A interrupt
output is known as INT, which is connected to the CPU (wait for
it) INTR, or to another 8259A's IRQ.
The 8 IRR bits are ANDed with the NOT of the IMR, giving the
interrupt request input to the priority arbitration logic.
Reading between the lines, there is an INT latch, which is set
by the OR of the bits of (IRR AND NOT IMR) higher than the
highest priority bit in the ISR.
On an original PC there are 8 possible interrupt sources IRQ0
to IRQ7, fed into one 8259A (I/O address #020..#03F).
On AT's and beyond, there are 16 possible interrupt sources
IRQ0 to IRQ15, fed into two 8259A's. One 8259A (known as #1,
I/O address #020..#03F) is the "Master" and the other is a
"Slave" (known as #2, I/O address #0A0..#0BF). Only the
Master's INT is connected to the CPU's INTR. The Slave's INT
is connected to the Master's IRQ2.
3. The Mechanisms
The PC sets the 8259A into:
* Edge Triggered Interrupts
* Cascaded (on AT and later) ; Single (on earlier machines)
* Not Special Fully Nested (to do with Slave 8259A, see below)
* Not Buffered Normal EOI (Not Automatic EOI on INTA)
With this in mind, we will start with the simple cases, and
work up.
3.1 One 8259A, All IRQ Unmasked, No Interrupts In Service
and None Active.
So we start from the simplest possible quiescent state. The
sequence of actions is as follows:
0 The ESR, ISR, IRR and IMR are all zero.
1 IRQ3 becomes active (goes to 1)
2 B3 of the ESR is set to 1
3 B3 of the IRR is set to 1
4 B3 of the IMR is 0, so the IRR B3 is passed to the
priority arbitration logic.
5 All bits of the ISR are 0 (no interrupts are in
service), so the priority arbitration logic sets the
INT latch -- so the INT output is set active.
6 Eventually the CPU issues the first of two INTA
cycles. The contents of the IRR are frozen. The
8259A selects the highest priority IRR (B3) and sets
the corresponding ISR (B3).
7 Setting B3 of the ISR clears B3 of the ESR.
8 The CPU issues the second of two INTA cycles. The
8259A issues the interrupt vector associated with the
highest priority ISR (B3). The contents of the IRR
are unfrozen.
9 The INT latch is cleared -- so the INT output is set
inactive.
10 B3 of the IRR is set to 0 (IRR is unfrozen and B3 of
ESR is zero).
11 At some time in the future, the CPU issues an EOI
command, which clears B3 of the ISR.
IRQ3 can remain active beyond step 10, without generating any
further interrupts -- because B3 of IRR has been cleared. To
produce another interrupt requires IRQ3 to go inactive (0), and
then active (1) again.
3.2 Meaning of "Edge Triggered Interrupt Mode"
The behavior of the ESR, IRR and ISR described above is what
happens in the famous Edge Triggered Interrupt Mode.
The purpose is to allow for IRQ signals to be short down/up
pulses. When the 8259A is reset the ESR is set to zero. An
upward transition of the IRQ sets the corresponding ESR bit to
1, which allows the IRQ state to be copied to the IRR --
provoking the interrupt. When the interrupt is acknowledged
the ISR bit is set, which resets the ESR bit, which forces the
IRR bit to zero -- irrespective of the IRQ. So even if IRQ is
still 1 when the ISR bit is cleared, at End of Interrupt, no
further interrupts will be generated.
3.3 What Happens if IRQ Changes with the Interrupt is In Service
It is clear what happens if IRQ does not do any further down/up
transitions until after EOI. It is OK for IRQ to go down
before EOI, but going up again is not explicitly described in
the manuals.
If a down/up IRQ transition cannot be prevented before EOI,
then it can be (reasonably safely) assumed that this will
generate a further interrupt after EOI -- provided the IRQ is
still up (active, 1) at EOI. Multiple down/up transitions can
be assumed to have the same effect.
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