Date: Tue, 14 May 1996 08:22:48 -0700 From: David Greenman <davidg@Root.COM> To: "matthew c. mead" <mmead@Glock.COM> Cc: joerg_wunsch@uriah.heep.sax.de, blh@nol.net, jgreco@brasil.moneng.mei.com, hackers@freebsd.org, hardware@freebsd.org Subject: Re: Triton chipset with 256k cache caches 32M only? Message-ID: <199605141522.IAA12962@Root.COM> In-Reply-To: Your message of "Tue, 14 May 1996 11:18:14 EDT." <199605141518.LAA08531@Glock.COM>
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>David Greenman writes: > >> > I'd really like to do ECC, I just don't have the money for >> >it right now. So does this ECC work the same as the ECC >> >on DEC Alphas? On the Alphas, you put in 5M for every 4M >> >of addressable ram. Is there a fifth simm slot on these >> >motherboards where a non ECC capable motherboard would have 4? > >> No, it uses the parity bits. Only 8 syndrome bits are needed >> for 64bit words. > > Hmm. So does that mean the ECC is limited to single (odd >number of) bit errors? ECC has single bit error correction and 2 bit error detection. Better than parity no matter how you slice it. -DG David Greenman Core-team/Principal Architect, The FreeBSD Project
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