From owner-freebsd-amd64@FreeBSD.ORG Wed Jun 17 17:57:09 2009 Return-Path: Delivered-To: freebsd-amd64@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 82DBD1065686 for ; Wed, 17 Jun 2009 17:57:09 +0000 (UTC) (envelope-from peter@wemm.org) Received: from mail-pz0-f171.google.com (mail-pz0-f171.google.com [209.85.222.171]) by mx1.freebsd.org (Postfix) with ESMTP id 6231B8FC19 for ; Wed, 17 Jun 2009 17:57:09 +0000 (UTC) (envelope-from peter@wemm.org) Received: by mail-pz0-f171.google.com with SMTP id 1so498975pzk.3 for ; Wed, 17 Jun 2009 10:57:09 -0700 (PDT) MIME-Version: 1.0 Received: by 10.142.133.19 with SMTP id g19mr386832wfd.327.1245259728427; Wed, 17 Jun 2009 10:28:48 -0700 (PDT) In-Reply-To: References: <500D653E-E4EE-4E49-94C3-E12754919DA4@netconsonance.com> Date: Wed, 17 Jun 2009 10:28:48 -0700 Message-ID: From: Peter Wemm To: Jo Rhett Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Cc: freebsd-amd64@freebsd.org Subject: Re: cpu does not support long mode X-BeenThere: freebsd-amd64@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to the AMD64 platform List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 17 Jun 2009 17:57:10 -0000 On Wed, Jun 17, 2009 at 10:26 AM, Jo Rhett wrote: >> >> On Wed, 17 Jun 2009, Jo Rhett wrote: >>> >>> I've got a Tyan S2720 with dual Xeon 2.4G dual-core processors here tha= t >>> I was going to test out 64-bit support with. =A0However, the system fai= ls >>> during boot of the 7.2-RELEASE CD with >>> >>> warning: module 'acpi' already loaded >>> Booting [/boot/kernel/kernel]... >>> CPU does not support long mode >>> OK > > On Jun 17, 2009, at 10:11 AM, Nate Eldredge wrote: >> >> Is that "does not" or "doesn't"? > > Probably "doesn't" -- I typed that in by hand and probably auto-corrected > ;-) > >> Do you have FreeBSD/i386 working on the machine? =A0If so, please instal= l >> the misc/cpuid port and post the output of `cpuid'. > > > Here it is: > > =A0eax in =A0 =A0eax =A0 =A0 =A0ebx =A0 =A0 =A0ecx =A0 =A0 =A0edx > 00000000 00000002 756e6547 6c65746e 49656e69 > 00000001 00000f27 0002080b 00000000 bfebfbff > 00000002 665b5001 00000000 00000000 007b7040 > 80000000 80000004 00000000 00000000 00000000 > 80000001 00000000 00000000 00000000 00000000 > 80000002 20202020 20202020 20202020 20202020 > 80000003 6e492020 286c6574 58202952 286e6f65 > 80000004 20294d54 20555043 30342e32 007a4847 > > Vendor ID: "GenuineIntel"; CPUID level 2 > > Intel-specific functions: > Version 00000f27: > Type 0 - Original OEM > Family 15 - Pentium 4 > Extended family 0 > Model 2 - Intel Pentium 4 processor (generic) or newer > Stepping 7 > Reserved 0 > > Brand index: 11 [Intel Xeon processor] > Extended brand string: " =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0Intel(R) Xeon= (TM) CPU 2.40GHz" > CLFLUSH instruction cache line size: 8 > Hyper threading siblings: 2 > > Feature flags: bfebfbff: > FPU =A0 =A0Floating Point Unit > VME =A0 =A0Virtual 8086 Mode Enhancements > DE =A0 =A0 Debugging Extensions > PSE =A0 =A0Page Size Extensions > TSC =A0 =A0Time Stamp Counter > MSR =A0 =A0Model Specific Registers > PAE =A0 =A0Physical Address Extension > MCE =A0 =A0Machine Check Exception > CX8 =A0 =A0COMPXCHG8B Instruction > APIC =A0 On-chip Advanced Programmable Interrupt Controller present and > enabled > SEP =A0 =A0Fast System Call > MTRR =A0 Memory Type Range Registers > PGE =A0 =A0PTE Global Flag > MCA =A0 =A0Machine Check Architecture > CMOV =A0 Conditional Move and Compare Instructions > FGPAT =A0Page Attribute Table > PSE-36 36-bit Page Size Extension > CLFSH =A0CFLUSH instruction > DS =A0 =A0 Debug store > ACPI =A0 Thermal Monitor and Clock Ctrl > MMX =A0 =A0MMX instruction set > FXSR =A0 Fast FP/MMX Streaming SIMD Extensions save/restore > SSE =A0 =A0Streaming SIMD Extensions instruction set > SSE2 =A0 SSE2 extensions > SS =A0 =A0 Self Snoop > HT =A0 =A0 Hyper Threading > TM =A0 =A0 Thermal monitor > 31 =A0 =A0 reserved > > TLB and cache info: > 50: Instruction TLB: 4KB and 2MB or 4MB pages, 64 entries > 5b: Data TLB: 4KB and 4MB pages, fully assoc., 64 entries > 66: 1st-level data cache: 8KB, 4-way set assoc, 64 byte line size > 40: No 2nd-level cache, or if 2nd-level cache exists, no 3rd-level cache > 70: Trace cache: 12K-micro-op, 4-way set assoc > 7b: 2 Yes, it is a 32-bit only cpu. --=20 Peter Wemm - peter@wemm.org; peter@FreeBSD.org; peter@yahoo-inc.com; KI6FJV "All of this is for nothing if we don't go to the stars" - JMS/B5 "If Java had true garbage collection, most programs would delete themselves upon execution." -- Robert Sewell