From owner-svn-src-all@FreeBSD.ORG Sat May 24 21:29:33 2014 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id D9E49B10; Sat, 24 May 2014 21:29:33 +0000 (UTC) Received: from mail-n.franken.de (drew.ipv6.franken.de [IPv6:2001:638:a02:a001:20e:cff:fe4a:feaa]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "mail-n.franken.de", Issuer "Thawte DV SSL CA" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 9996A2F89; Sat, 24 May 2014 21:29:33 +0000 (UTC) Received: from [192.168.1.200] (p5481968B.dip0.t-ipconnect.de [84.129.150.139]) (Authenticated sender: macmic) by mail-n.franken.de (Postfix) with ESMTP id A0A561C1049B1; Sat, 24 May 2014 23:29:29 +0200 (CEST) Content-Type: text/plain; charset=windows-1252 Mime-Version: 1.0 (Mac OS X Mail 7.3 \(1878.2\)) Subject: Re: svn commit: r266083 - in head/sys/arm: arm include From: Michael Tuexen In-Reply-To: <20140524220215.79032279@bender.Home> Date: Sat, 24 May 2014 23:29:28 +0200 Content-Transfer-Encoding: quoted-printable Message-Id: <61D0CEF5-6D52-4C3B-8727-8474ECD045EA@freebsd.org> References: <201405141911.s4EJBFZZ097826@svn.freebsd.org> <537D0952.2040001@selasky.org> <7610C8E6-3F01-4317-BC1A-67645A162CD7@FreeBSD.org> <083E3DCB-F49A-4757-9CF8-689D04267E26@freebsd.org> <20140524220215.79032279@bender.Home> To: Andrew Turner X-Mailer: Apple Mail (2.1878.2) Cc: Hans Petter Selasky , svn-src-head@freebsd.org, svn-src-all@freebsd.org, src-committers@freebsd.org, Mark R V Murray X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 24 May 2014 21:29:34 -0000 On 24 May 2014, at 23:02, Andrew Turner wrote: > On Sat, 24 May 2014 21:09:56 +0200 > Michael Tuexen wrote: >=20 >> On 22 May 2014, at 09:09, Mark R V Murray wrote: >>=20 >>>=20 >>> On 21 May 2014, at 21:15, Hans Petter Selasky >>> wrote: >>>=20 >>>> On 05/14/14 21:11, Mark Murray wrote: >>>>> Author: markm >>>>> Date: Wed May 14 19:11:15 2014 >>>>> New Revision: 266083 >>>>> URL: http://svnweb.freebsd.org/changeset/base/266083 >>>>>=20 >>>>> Log: >>>>> Give suitably-endowed ARMs a register similar to the x86 TSC >>>>> register. >>>>>=20 >>>>=20 >>>> Hi, >>>>=20 >>>> Regression issue: >>>> This commit prevents RPI-B from booting. >>>=20 >>> Thanks, I=92ll look at it ASAP. >> Doesn't the ARM1176 use for example >> MRC p15, 0, , c15, c12, 1 ; Read Cycle Counter Register >> to read the value, whereas the=20 >> you use=20 >> __asm __volatile("mrc p15, 0, %0, c9, c13, 0": "=3Dr" (ccnt)); >=20 > On ARMv6 there is no guarantee of a cycle count register. On the > ARM1176 there is one in an implementation defined section of the = system > control coprocessor. This is the c15 section above, and is accessible > as shown. >=20 > On ARMv7 there are optional performance monitor extensions. These are > in parts of the c9 section of the coprocessor. As it is optional there > is no requirement for implementers to include this functionality, > however I would expect the ARM designs to include it, and most non-ARM > designs are likely aiming for performance so will also include them. >=20 > If the ARMv7 processor has the performance extensions the existing = code > appears correct to retrieve it. The code is #ifdef as #if defined(CPU_ARM1136) || defined(CPU_ARM1176) \ || defined(CPU_MV_PJ4B) \ || defined(CPU_CORTEXA) || defined(CPU_KRAIT) Isn't the Raspberry Pi defining CPU_ARM1176 and using ARMv6? So can we = use the same code for all plattforms in the #ifdef? Best regards Michael >=20 > Andrew >=20 >=20