From owner-svn-src-all@FreeBSD.ORG Sun Jul 8 21:21:45 2012 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id D619F1065674; Sun, 8 Jul 2012 21:21:45 +0000 (UTC) (envelope-from rwatson@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id C04948FC0A; Sun, 8 Jul 2012 21:21:45 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.4/8.14.4) with ESMTP id q68LLjbX075271; Sun, 8 Jul 2012 21:21:45 GMT (envelope-from rwatson@svn.freebsd.org) Received: (from rwatson@localhost) by svn.freebsd.org (8.14.4/8.14.4/Submit) id q68LLjZq075268; Sun, 8 Jul 2012 21:21:45 GMT (envelope-from rwatson@svn.freebsd.org) Message-Id: <201207082121.q68LLjZq075268@svn.freebsd.org> From: Robert Watson Date: Sun, 8 Jul 2012 21:21:45 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-9@freebsd.org X-SVN-Group: stable-9 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r238266 - stable/9/sys/mips/mips X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jul 2012 21:21:46 -0000 Author: rwatson Date: Sun Jul 8 21:21:45 2012 New Revision: 238266 URL: http://svn.freebsd.org/changeset/base/238266 Log: Merge r231712 from head to stable/9: When initialising the CP0 status register during boot on 64-bit MIPS, set all three of the kernel, supervisor, and user-mode 64-bit mode flags. While FreeBSD does not currently use the supervisor ring (and hence this is effectively a NOP on most systems), doing this avoids triggering an exception on 64-bit MIPS CPUs that don't support 32-bit compatibility mode, and therefore don't allow clearing the SX bit. Reviewed by: gonzo Sponsored by: DARPA, SRI International Approved by: re (kib) Modified: stable/9/sys/mips/mips/locore.S Directory Properties: stable/9/sys/ (props changed) Modified: stable/9/sys/mips/mips/locore.S ============================================================================== --- stable/9/sys/mips/mips/locore.S Sun Jul 8 21:13:04 2012 (r238265) +++ stable/9/sys/mips/mips/locore.S Sun Jul 8 21:21:45 2012 (r238266) @@ -118,7 +118,7 @@ VECTOR(_locore, unknown) */ li t1, MIPS_SR_COP_1_BIT #ifdef __mips_n64 - or t1, MIPS_SR_KX | MIPS_SR_UX + or t1, MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX #endif #endif /*