From owner-freebsd-current@FreeBSD.ORG Wed Dec 7 14:06:53 2005 Return-Path: X-Original-To: freebsd-current@freebsd.org Delivered-To: freebsd-current@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 6929F16A422 for ; Wed, 7 Dec 2005 14:06:53 +0000 (GMT) (envelope-from jhb@freebsd.org) Received: from speedfactory.net (mail6.speedfactory.net [66.23.216.219]) by mx1.FreeBSD.org (Postfix) with ESMTP id C77C543D93 for ; Wed, 7 Dec 2005 14:06:22 +0000 (GMT) (envelope-from jhb@freebsd.org) Received: from server.baldwin.cx (unverified [66.23.211.162]) by speedfactory.net (SurgeMail 3.5b3) with ESMTP id 3317323 for multiple; Wed, 07 Dec 2005 09:08:12 -0500 Received: from zion.baldwin.cx (zion.baldwin.cx [192.168.0.7]) (authenticated bits=0) by server.baldwin.cx (8.13.1/8.13.1) with ESMTP id jB7E66Dd056676; Wed, 7 Dec 2005 09:06:06 -0500 (EST) (envelope-from jhb@freebsd.org) From: John Baldwin To: freebsd-current@freebsd.org Date: Wed, 7 Dec 2005 09:06:03 -0500 User-Agent: KMail/1.8.3 References: <018e01c5fafe$c9154a20$642a15ac@smiley> In-Reply-To: <018e01c5fafe$c9154a20$642a15ac@smiley> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Message-Id: <200512070906.05117.jhb@freebsd.org> X-Spam-Status: No, score=-2.8 required=4.2 tests=ALL_TRUSTED autolearn=failed version=3.0.2 X-Spam-Checker-Version: SpamAssassin 3.0.2 (2004-11-16) on server.baldwin.cx X-Server: High Performance Mail Server - http://surgemail.com r=1653887525 Cc: Darren Pilgrim Subject: Re: can someone explain...[ PCI interrupts] X-BeenThere: freebsd-current@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Discussions about the use of FreeBSD-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 07 Dec 2005 14:06:53 -0000 On Wednesday 07 December 2005 02:20 am, Darren Pilgrim wrote: > From: John Baldwin > > > The reason [for masking interrupts] is that PCI interrupts are level > > triggered, so they won't "shut up" until the ISR has run and pacified > > the PCI device. > > But PCI interrupts can be programmed either level- or edge-triggered, so > wouldn't programming to edge-triggered interrupts solve the "they won't > shut up" issue? No, PCI interrupts are level triggered. Individual APIC pins can be=20 programmed to be edge-triggered, sure. However, then interrupts stop worki= ng=20 if 2 devices are sharing a line and one interrupts after the other has=20 already interrupted and after the second device's ISR has already run. In= =20 this case, the ithread will finish and go back to sleep waiting for an=20 interrupt. However, since the ISR for the second device wasn't run after=20 that device asserted its interrupt pin, the second device will keep the pin= =20 pulled low forever, so there will never be a hi -> low transition that the= =20 APIC pin would post an interrupt for and that intpin and all attached devic= es=20 are effectively dead. =2D-=20 John Baldwin =A0<>< =A0http://www.FreeBSD.org/~jhb/ "Power Users Use the Power to Serve" =A0=3D =A0http://www.FreeBSD.org