From owner-cvs-src@FreeBSD.ORG Sun Apr 13 07:44:56 2008 Return-Path: Delivered-To: cvs-src@FreeBSD.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 3D8A11065672; Sun, 13 Apr 2008 07:44:56 +0000 (UTC) (envelope-from imp@FreeBSD.org) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id 236A08FC13; Sun, 13 Apr 2008 07:44:56 +0000 (UTC) (envelope-from imp@FreeBSD.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.1/8.14.1) with ESMTP id m3D7iuI0088952; Sun, 13 Apr 2008 07:44:56 GMT (envelope-from imp@repoman.freebsd.org) Received: (from imp@localhost) by repoman.freebsd.org (8.14.1/8.14.1/Submit) id m3D7iuVo088948; Sun, 13 Apr 2008 07:44:56 GMT (envelope-from imp) Message-Id: <200804130744.m3D7iuVo088948@repoman.freebsd.org> From: Warner Losh Date: Sun, 13 Apr 2008 07:44:55 +0000 (UTC) To: src-committers@FreeBSD.org, cvs-src@FreeBSD.org, cvs-all@FreeBSD.org X-FreeBSD-CVS-Branch: HEAD Cc: Subject: cvs commit: src/sys/mips/mips32/adm5120 adm5120_machdep.c adm5120reg.h admpci.c console.c files.adm5120 if_admsw.c if_admswreg.h if_admswvar.h obio.c obiovar.h std.adm5120 uart_bus_adm5120.c uart_cpu_adm5120.c uart_dev_adm5120.c uart_dev_adm5120.h ... X-BeenThere: cvs-src@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: CVS commit messages for the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 13 Apr 2008 07:44:56 -0000 imp 2008-04-13 07:44:55 UTC FreeBSD src repository Added files: sys/mips/mips32/adm5120 adm5120_machdep.c adm5120reg.h admpci.c console.c files.adm5120 if_admsw.c if_admswreg.h if_admswvar.h obio.c obiovar.h std.adm5120 uart_bus_adm5120.c uart_cpu_adm5120.c uart_dev_adm5120.c uart_dev_adm5120.h sys/mips/mips32/idt files.idt idt_machdep.c idtpci.c idtreg.h if_kr.c if_krreg.h obio.c obiovar.h std.idt uart_bus_rc32434.c uart_cpu_rc32434.c sys/mips/mips32/malta files.malta gt.c gt_pci.c gtreg.h gtvar.h malta_machdep.c maltareg.h obio.c obiovar.h std.malta uart_bus_maltausart.c uart_cpu_maltausart.c yamon.c yamon.h sys/mips/mips32/sentry5 files.sentry5 obio.c obiovar.h s5_machdep.c s5reg.h siba_cc.c siba_mips.c siba_sdram.c uart_bus_sbusart.c uart_cpu_sbusart.c Log: FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett. Revision Changes Path 1.1 +157 -0 src/sys/mips/mips32/adm5120/adm5120_machdep.c (new) 1.1 +294 -0 src/sys/mips/mips32/adm5120/adm5120reg.h (new) 1.1 +503 -0 src/sys/mips/mips32/adm5120/admpci.c (new) 1.1 +93 -0 src/sys/mips/mips32/adm5120/console.c (new) 1.1 +11 -0 src/sys/mips/mips32/adm5120/files.adm5120 (new) 1.1 +1339 -0 src/sys/mips/mips32/adm5120/if_admsw.c (new) 1.1 +678 -0 src/sys/mips/mips32/adm5120/if_admswreg.h (new) 1.1 +212 -0 src/sys/mips/mips32/adm5120/if_admswvar.h (new) 1.1 +510 -0 src/sys/mips/mips32/adm5120/obio.c (new) 1.1 +66 -0 src/sys/mips/mips32/adm5120/obiovar.h (new) 1.1 +10 -0 src/sys/mips/mips32/adm5120/std.adm5120 (new) 1.1 +93 -0 src/sys/mips/mips32/adm5120/uart_bus_adm5120.c (new) 1.1 +83 -0 src/sys/mips/mips32/adm5120/uart_cpu_adm5120.c (new) 1.1 +452 -0 src/sys/mips/mips32/adm5120/uart_dev_adm5120.c (new) 1.1 +80 -0 src/sys/mips/mips32/adm5120/uart_dev_adm5120.h (new) 1.1 +8 -0 src/sys/mips/mips32/idt/files.idt (new) 1.1 +188 -0 src/sys/mips/mips32/idt/idt_machdep.c (new) 1.1 +565 -0 src/sys/mips/mips32/idt/idtpci.c (new) 1.1 +153 -0 src/sys/mips/mips32/idt/idtreg.h (new) 1.1 +1615 -0 src/sys/mips/mips32/idt/if_kr.c (new) 1.1 +284 -0 src/sys/mips/mips32/idt/if_krreg.h (new) 1.1 +514 -0 src/sys/mips/mips32/idt/obio.c (new) 1.1 +67 -0 src/sys/mips/mips32/idt/obiovar.h (new) 1.1 +5 -0 src/sys/mips/mips32/idt/std.idt (new) 1.1 +100 -0 src/sys/mips/mips32/idt/uart_bus_rc32434.c (new) 1.1 +85 -0 src/sys/mips/mips32/idt/uart_cpu_rc32434.c (new) 1.1 +9 -0 src/sys/mips/mips32/malta/files.malta (new) 1.1 +131 -0 src/sys/mips/mips32/malta/gt.c (new) 1.1 +723 -0 src/sys/mips/mips32/malta/gt_pci.c (new) 1.1 +126 -0 src/sys/mips/mips32/malta/gtreg.h (new) 1.1 +36 -0 src/sys/mips/mips32/malta/gtvar.h (new) 1.1 +305 -0 src/sys/mips/mips32/malta/malta_machdep.c (new) 1.1 +243 -0 src/sys/mips/mips32/malta/maltareg.h (new) 1.1 +185 -0 src/sys/mips/mips32/malta/obio.c (new) 1.1 +58 -0 src/sys/mips/mips32/malta/obiovar.h (new) 1.1 +9 -0 src/sys/mips/mips32/malta/std.malta (new) 1.1 +98 -0 src/sys/mips/mips32/malta/uart_bus_maltausart.c (new) 1.1 +82 -0 src/sys/mips/mips32/malta/uart_cpu_maltausart.c (new) 1.1 +65 -0 src/sys/mips/mips32/malta/yamon.c (new) 1.1 +93 -0 src/sys/mips/mips32/malta/yamon.h (new) 1.1 +14 -0 src/sys/mips/mips32/sentry5/files.sentry5 (new) 1.1 +187 -0 src/sys/mips/mips32/sentry5/obio.c (new) 1.1 +58 -0 src/sys/mips/mips32/sentry5/obiovar.h (new) 1.1 +241 -0 src/sys/mips/mips32/sentry5/s5_machdep.c (new) 1.1 +58 -0 src/sys/mips/mips32/sentry5/s5reg.h (new) 1.1 +154 -0 src/sys/mips/mips32/sentry5/siba_cc.c (new) 1.1 +113 -0 src/sys/mips/mips32/sentry5/siba_mips.c (new) 1.1 +114 -0 src/sys/mips/mips32/sentry5/siba_sdram.c (new) 1.1 +95 -0 src/sys/mips/mips32/sentry5/uart_bus_sbusart.c (new) 1.1 +82 -0 src/sys/mips/mips32/sentry5/uart_cpu_sbusart.c (new)