From owner-cvs-src-old@FreeBSD.ORG Thu Aug 12 10:09:51 2010 Return-Path: Delivered-To: cvs-src-old@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id ECDAF106570E for ; Thu, 12 Aug 2010 10:09:51 +0000 (UTC) (envelope-from jchandra@FreeBSD.org) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id DA7B48FC1A for ; Thu, 12 Aug 2010 10:09:51 +0000 (UTC) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.4/8.14.4) with ESMTP id o7CA9pnZ023292 for ; Thu, 12 Aug 2010 10:09:51 GMT (envelope-from jchandra@repoman.freebsd.org) Received: (from svn2cvs@localhost) by repoman.freebsd.org (8.14.4/8.14.4/Submit) id o7CA9pIl023291 for cvs-src-old@freebsd.org; Thu, 12 Aug 2010 10:09:51 GMT (envelope-from jchandra@repoman.freebsd.org) Message-Id: <201008121009.o7CA9pIl023291@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: svn2cvs set sender to jchandra@repoman.freebsd.org using -f From: "Jayachandran C." Date: Thu, 12 Aug 2010 10:09:28 +0000 (UTC) To: cvs-src-old@freebsd.org X-FreeBSD-CVS-Branch: HEAD Subject: cvs commit: src/sys/mips/include pmap.h src/sys/mips/mips pmap.c trap.c X-BeenThere: cvs-src-old@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: **OBSOLETE** CVS commit messages for the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Aug 2010 10:09:52 -0000 jchandra 2010-08-12 10:09:28 UTC FreeBSD src repository Modified files: sys/mips/include pmap.h sys/mips/mips pmap.c trap.c Log: SVN rev 211217 on 2010-08-12 10:09:28Z by jchandra Implement pmap changes suggested by alc@: 1. Move dirty bit emulation code that is duplicted for kernel and user in trap.c to a function pmap_emulate_modified() in pmap.c. 2. While doing dirty bit emulation, it is not necessary to update the TLB entry on all CPUs using smp_rendezvous(), we can just update the TLB entry on the current CPU, and let the other CPUs update their TLB entry lazily if they get an exception. Reviewed by: alc, neel Revision Changes Path 1.19 +1 -3 src/sys/mips/include/pmap.h 1.78 +42 -7 src/sys/mips/mips/pmap.c 1.21 +9 -68 src/sys/mips/mips/trap.c