From owner-freebsd-current@FreeBSD.ORG Thu Apr 10 21:45:43 2008 Return-Path: Delivered-To: current@FreeBSD.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 592EC106564A; Thu, 10 Apr 2008 21:45:43 +0000 (UTC) (envelope-from phk@critter.freebsd.dk) Received: from phk.freebsd.dk (phk.freebsd.dk [130.225.244.222]) by mx1.freebsd.org (Postfix) with ESMTP id 1B2DE8FC23; Thu, 10 Apr 2008 21:45:43 +0000 (UTC) (envelope-from phk@critter.freebsd.dk) Received: from critter.freebsd.dk (unknown [192.168.61.3]) by phk.freebsd.dk (Postfix) with ESMTP id AE2F317105; Thu, 10 Apr 2008 21:45:41 +0000 (UTC) Received: from critter.freebsd.dk (localhost [127.0.0.1]) by critter.freebsd.dk (8.14.2/8.14.2) with ESMTP id m3ALjfjq001249; Thu, 10 Apr 2008 21:45:41 GMT (envelope-from phk@critter.freebsd.dk) To: Maxim Sobolev From: "Poul-Henning Kamp" In-Reply-To: Your message of "Thu, 10 Apr 2008 13:52:28 MST." <47FE7E0C.4070801@FreeBSD.org> Date: Thu, 10 Apr 2008 21:45:41 +0000 Message-ID: <1248.1207863941@critter.freebsd.dk> Sender: phk@critter.freebsd.dk Cc: gnn@FreeBSD.org, Kris Kennaway , current@FreeBSD.org Subject: Re: TSC Timecounter and multi-core/SMP X-BeenThere: freebsd-current@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Discussions about the use of FreeBSD-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 10 Apr 2008 21:45:43 -0000 In message <47FE7E0C.4070801@FreeBSD.org>, Maxim Sobolev writes: >Kris Kennaway wrote: >> gnn@freebsd.org wrote: >>> Howdy, >>> >>> Is the TSC timecounter synchronized across multiple cores and/or >>> processors? A quick search seems to indicate it's not but I'd like to >>> find a definitive reference on the TSC. >> >> Modern Intel systems tend to be synchronized, in my experience. > >I really doubt they are. As far as I know newest milti-core chips can >modulate frequency of even suspend individual cores independently of >each other, which would make such synchronization difficult to maintain >if the power management is on. P4 (and I think most newer chips) have a TSC that runs independent of the cpu clock frequency, and supposedly, always at constant rate. -- Poul-Henning Kamp | UNIX since Zilog Zeus 3.20 phk@FreeBSD.ORG | TCP/IP since RFC 956 FreeBSD committer | BSD since 4.3-tahoe Never attribute to malice what can adequately be explained by incompetence.