From owner-svn-soc-all@freebsd.org Mon Aug 31 08:05:39 2015 Return-Path: Delivered-To: svn-soc-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id AEB5C9C6A0E for ; Mon, 31 Aug 2015 08:05:39 +0000 (UTC) (envelope-from mihai@FreeBSD.org) Received: from socsvn.freebsd.org (socsvn.freebsd.org [IPv6:2001:1900:2254:206a::50:2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 85C9E1C71 for ; Mon, 31 Aug 2015 08:05:39 +0000 (UTC) (envelope-from mihai@FreeBSD.org) Received: from socsvn.freebsd.org ([127.0.1.124]) by socsvn.freebsd.org (8.15.2/8.15.2) with ESMTP id t7V85d2Q046333 for ; Mon, 31 Aug 2015 08:05:39 GMT (envelope-from mihai@FreeBSD.org) Received: (from www@localhost) by socsvn.freebsd.org (8.15.2/8.15.2/Submit) id t7V85cVr046258 for svn-soc-all@FreeBSD.org; Mon, 31 Aug 2015 08:05:38 GMT (envelope-from mihai@FreeBSD.org) Date: Mon, 31 Aug 2015 08:05:38 GMT Message-Id: <201508310805.t7V85cVr046258@socsvn.freebsd.org> X-Authentication-Warning: socsvn.freebsd.org: www set sender to mihai@FreeBSD.org using -f From: mihai@FreeBSD.org To: svn-soc-all@FreeBSD.org Subject: socsvn commit: r290376 - soc2015/mihai/bhyve-on-arm-head/sys/arm/arm MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-soc-all@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: SVN commit messages for the entire Summer of Code repository List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 31 Aug 2015 08:05:39 -0000 Author: mihai Date: Mon Aug 31 08:05:38 2015 New Revision: 290376 URL: http://svnweb.FreeBSD.org/socsvn/?view=rev&rev=290376 Log: sys: arm: arm: gic.c: active-high-level and rising-edge only is for SPI only Modified: soc2015/mihai/bhyve-on-arm-head/sys/arm/arm/gic.c Modified: soc2015/mihai/bhyve-on-arm-head/sys/arm/arm/gic.c ============================================================================== --- soc2015/mihai/bhyve-on-arm-head/sys/arm/arm/gic.c Mon Aug 31 08:04:15 2015 (r290375) +++ soc2015/mihai/bhyve-on-arm-head/sys/arm/arm/gic.c Mon Aug 31 08:05:38 2015 (r290376) @@ -62,6 +62,7 @@ #ifdef VMM_ARM_VGIC { SYS_RES_MEMORY, 2, RF_ACTIVE }, /* Virtual Interface Control */ { SYS_RES_MEMORY, 3, RF_ACTIVE }, /* Virtual CPU interface */ +// { SYS_RES_IRQ, 4, RF_ACTIVE }, /* vGIC maintenance interrupt */ #endif { -1, 0 } }; @@ -152,10 +153,6 @@ *trig = INTR_TRIGGER_CONFORM; *pol = INTR_POLARITY_CONFORM; } else { - if (fdt32_to_cpu(intr[0]) == 0) - *interrupt = fdt32_to_cpu(intr[1]) + GIC_FIRST_SPI; - else - *interrupt = fdt32_to_cpu(intr[1]) + GIC_FIRST_PPI; /* * In intr[2], bits[3:0] are trigger type and level flags. * 1 = low-to-high edge triggered @@ -164,13 +161,19 @@ * 8 = active low level-sensitive * The hardware only supports active-high-level or rising-edge. */ - if (fdt32_to_cpu(intr[2]) & 0x0a) { - printf("unsupported trigger/polarity configuration " - "0x%2x\n", fdt32_to_cpu(intr[2]) & 0x0f); - return (ENOTSUP); + if (fdt32_to_cpu(intr[0]) == 0) { + if (fdt32_to_cpu(intr[2]) & 0x0a) { + printf("unsupported trigger/polarity configuration " + "0x%2x\n", fdt32_to_cpu(intr[2]) & 0x0f); + return (ENOTSUP); + } + *interrupt = fdt32_to_cpu(intr[1]) + GIC_FIRST_SPI; + } else { + *interrupt = fdt32_to_cpu(intr[1]) + GIC_FIRST_PPI; } + *pol = INTR_POLARITY_CONFORM; - if (fdt32_to_cpu(intr[2]) & 0x01) + if (fdt32_to_cpu(intr[2]) & 0x03) *trig = INTR_TRIGGER_EDGE; else *trig = INTR_TRIGGER_LEVEL;