From owner-svn-src-stable@freebsd.org Sat Apr 23 07:36:14 2016 Return-Path: Delivered-To: svn-src-stable@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id C1C2AB19E0D; Sat, 23 Apr 2016 07:36:14 +0000 (UTC) (envelope-from kib@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 9C82A13C4; Sat, 23 Apr 2016 07:36:14 +0000 (UTC) (envelope-from kib@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u3N7aD4Q072182; Sat, 23 Apr 2016 07:36:13 GMT (envelope-from kib@FreeBSD.org) Received: (from kib@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u3N7aDRf072180; Sat, 23 Apr 2016 07:36:13 GMT (envelope-from kib@FreeBSD.org) Message-Id: <201604230736.u3N7aDRf072180@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: kib set sender to kib@FreeBSD.org using -f From: Konstantin Belousov Date: Sat, 23 Apr 2016 07:36:13 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-10@freebsd.org Subject: svn commit: r298506 - in stable/10/sys/x86: include x86 X-SVN-Group: stable-10 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-stable@freebsd.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: SVN commit messages for all the -stable branches of the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 23 Apr 2016 07:36:14 -0000 Author: kib Date: Sat Apr 23 07:36:13 2016 New Revision: 298506 URL: https://svnweb.freebsd.org/changeset/base/298506 Log: MFC r298101: Add x86 CPU features definitions published in the Intel SDM rev. 58. Modified: stable/10/sys/x86/include/specialreg.h stable/10/sys/x86/x86/identcpu.c Directory Properties: stable/10/ (props changed) Modified: stable/10/sys/x86/include/specialreg.h ============================================================================== --- stable/10/sys/x86/include/specialreg.h Sat Apr 23 07:28:32 2016 (r298505) +++ stable/10/sys/x86/include/specialreg.h Sat Apr 23 07:36:13 2016 (r298506) @@ -331,6 +331,7 @@ */ #define CPUID_STDEXT_FSGSBASE 0x00000001 #define CPUID_STDEXT_TSC_ADJUST 0x00000002 +#define CPUID_STDEXT_SGX 0x00000004 #define CPUID_STDEXT_BMI1 0x00000008 #define CPUID_STDEXT_HLE 0x00000010 #define CPUID_STDEXT_AVX2 0x00000020 @@ -340,7 +341,10 @@ #define CPUID_STDEXT_ERMS 0x00000200 #define CPUID_STDEXT_INVPCID 0x00000400 #define CPUID_STDEXT_RTM 0x00000800 +#define CPUID_STDEXT_PQM 0x00001000 +#define CPUID_STDEXT_NFPUSG 0x00002000 #define CPUID_STDEXT_MPX 0x00004000 +#define CPUID_STDEXT_PQE 0x00008000 #define CPUID_STDEXT_AVX512F 0x00010000 #define CPUID_STDEXT_RDSEED 0x00040000 #define CPUID_STDEXT_ADX 0x00080000 @@ -353,6 +357,16 @@ #define CPUID_STDEXT_SHA 0x20000000 /* + * CPUID instruction 7 Structured Extended Features, leaf 0 ecx info + */ +#define CPUID_STDEXT2_PREFETCHWT1 0x00000001 +#define CPUID_STDEXT2_UMIP 0x00000004 +#define CPUID_STDEXT2_PKU 0x00000008 +#define CPUID_STDEXT2_OSPKE 0x00000010 +#define CPUID_STDEXT2_RDPID 0x00400000 +#define CPUID_STDEXT2_SGXLC 0x40000000 + +/* * CPUID manufacturers identifiers */ #define AMD_VENDOR_ID "AuthenticAMD" Modified: stable/10/sys/x86/x86/identcpu.c ============================================================================== --- stable/10/sys/x86/x86/identcpu.c Sat Apr 23 07:28:32 2016 (r298505) +++ stable/10/sys/x86/x86/identcpu.c Sat Apr 23 07:36:13 2016 (r298506) @@ -888,6 +888,7 @@ printcpuinfo(void) /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ "\001FSGSBASE" "\002TSCADJ" + "\003SGX" /* Bit Manipulation Instructions */ "\004BMI1" /* Hardware Lock Elision */ @@ -907,9 +908,9 @@ printcpuinfo(void) "\014RTM" "\015PQM" "\016NFPUSG" - "\020PQE" /* Intel Memory Protection Extensions */ "\017MPX" + "\020PQE" /* AVX512 Foundation */ "\021AVX512F" /* Enhanced NRBG */ @@ -932,8 +933,11 @@ printcpuinfo(void) cpu_stdext_feature2, "\020" "\001PREFETCHWT1" + "\003UMIP" "\004PKU" "\005OSPKE" + "\027RDPID" + "\037SGXLC" ); } @@ -1880,7 +1884,10 @@ print_INTEL_TLB(u_int data) printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n"); break; case 0x63: - printf("Data TLB: 1 GByte pages, 4-way set associative, 4 entries\n"); + printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n"); + break; + case 0x64: + printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n"); break; case 0x66: printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n"); @@ -1996,6 +2003,9 @@ print_INTEL_TLB(u_int data) case 0xc3: printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n"); break; + case 0xc4: + printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n"); + break; case 0xca: printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n"); break;