From owner-svn-src-all@FreeBSD.ORG Tue Oct 15 01:35:50 2013 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTP id 15B268A2; Tue, 15 Oct 2013 01:35:50 +0000 (UTC) (envelope-from adrian@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id 03D272641; Tue, 15 Oct 2013 01:35:50 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.7/8.14.7) with ESMTP id r9F1ZnsZ098312; Tue, 15 Oct 2013 01:35:49 GMT (envelope-from adrian@svn.freebsd.org) Received: (from adrian@localhost) by svn.freebsd.org (8.14.7/8.14.5/Submit) id r9F1ZnCe098308; Tue, 15 Oct 2013 01:35:49 GMT (envelope-from adrian@svn.freebsd.org) Message-Id: <201310150135.r9F1ZnCe098308@svn.freebsd.org> From: Adrian Chadd Date: Tue, 15 Oct 2013 01:35:49 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r256487 - head/sys/mips/atheros X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 15 Oct 2013 01:35:50 -0000 Author: adrian Date: Tue Oct 15 01:35:48 2013 New Revision: 256487 URL: http://svnweb.freebsd.org/changeset/base/256487 Log: Add new features - an MDIO clock, WMAC reset, GMAC reset and ethernet switch reset/initialise functions. The AR934x and QC955x SoCs both have a configurable MDIO base clock. The others have the MDIO clock use the same clock as the system reference clock, whatever that may be. Tested: * AR9344 SoC TODO: * mips24k - AR933x would be fine for now, just to ensure that things are sane. Modified: head/sys/mips/atheros/ar71xx_chip.c head/sys/mips/atheros/ar71xx_cpudef.h head/sys/mips/atheros/ar724x_chip.c head/sys/mips/atheros/ar91xx_chip.c Modified: head/sys/mips/atheros/ar71xx_chip.c ============================================================================== --- head/sys/mips/atheros/ar71xx_chip.c Tue Oct 15 00:26:02 2013 (r256486) +++ head/sys/mips/atheros/ar71xx_chip.c Tue Oct 15 01:35:48 2013 (r256487) @@ -81,6 +81,7 @@ uint32_t u_ar71xx_ddr_freq; uint32_t u_ar71xx_uart_freq; uint32_t u_ar71xx_wdt_freq; uint32_t u_ar71xx_refclk; +uint32_t u_ar71xx_mdio_freq; static void ar71xx_chip_detect_mem_size(void) @@ -94,7 +95,7 @@ ar71xx_chip_detect_sys_frequency(void) uint32_t freq; uint32_t div; - u_ar71xx_refclk = AR71XX_BASE_FREQ; + u_ar71xx_mdio_freq = u_ar71xx_refclk = AR71XX_BASE_FREQ; pll = ATH_READ_REG(AR71XX_PLL_REG_CPU_CONFIG); Modified: head/sys/mips/atheros/ar71xx_cpudef.h ============================================================================== --- head/sys/mips/atheros/ar71xx_cpudef.h Tue Oct 15 00:26:02 2013 (r256486) +++ head/sys/mips/atheros/ar71xx_cpudef.h Tue Oct 15 01:35:48 2013 (r256487) @@ -57,6 +57,12 @@ struct ar71xx_cpu_def { * each chip. */ void (* ar71xx_chip_init_usb_peripheral) (void); + + void (* ar71xx_chip_reset_ethernet_switch) (void); + + void (* ar71xx_chip_reset_wmac) (void); + + void (* ar71xx_chip_init_gmac) (void); }; extern struct ar71xx_cpu_def * ar71xx_cpu_ops; @@ -111,6 +117,24 @@ static inline void ar71xx_init_usb_perip ar71xx_cpu_ops->ar71xx_chip_init_usb_peripheral(); } +static inline void ar71xx_reset_ethernet_switch(void) +{ + if (ar71xx_cpu_ops->ar71xx_chip_reset_ethernet_switch) + ar71xx_cpu_ops->ar71xx_chip_reset_ethernet_switch(); +} + +static inline void ar71xx_reset_wmac(void) +{ + if (ar71xx_cpu_ops->ar71xx_chip_reset_wmac) + ar71xx_cpu_ops->ar71xx_chip_reset_wmac(); +} + +static inline void ar71xx_init_gmac(void) +{ + if (ar71xx_cpu_ops->ar71xx_chip_init_gmac) + ar71xx_cpu_ops->ar71xx_chip_init_gmac(); +} + static inline void ar71xx_device_ddr_flush_ip2(void) { ar71xx_cpu_ops->ar71xx_chip_ddr_flush_ip2(); @@ -123,6 +147,7 @@ extern uint32_t u_ar71xx_ahb_freq; extern uint32_t u_ar71xx_ddr_freq; extern uint32_t u_ar71xx_uart_freq; extern uint32_t u_ar71xx_wdt_freq; +extern uint32_t u_ar71xx_mdio_freq; static inline uint64_t ar71xx_refclk(void) { return u_ar71xx_refclk; } static inline uint64_t ar71xx_cpu_freq(void) { return u_ar71xx_cpu_freq; } @@ -130,5 +155,6 @@ static inline uint64_t ar71xx_ahb_freq(v static inline uint64_t ar71xx_ddr_freq(void) { return u_ar71xx_ddr_freq; } static inline uint64_t ar71xx_uart_freq(void) { return u_ar71xx_uart_freq; } static inline uint64_t ar71xx_wdt_freq(void) { return u_ar71xx_wdt_freq; } +static inline uint64_t ar71xx_mdio_freq(void) { return u_ar71xx_mdio_freq; } #endif Modified: head/sys/mips/atheros/ar724x_chip.c ============================================================================== --- head/sys/mips/atheros/ar724x_chip.c Tue Oct 15 00:26:02 2013 (r256486) +++ head/sys/mips/atheros/ar724x_chip.c Tue Oct 15 01:35:48 2013 (r256487) @@ -73,7 +73,7 @@ ar724x_chip_detect_sys_frequency(void) uint32_t freq; uint32_t div; - u_ar71xx_refclk = AR724X_BASE_FREQ; + u_ar71xx_mdio_freq = u_ar71xx_refclk = AR724X_BASE_FREQ; pll = ATH_READ_REG(AR724X_PLL_REG_CPU_CONFIG); Modified: head/sys/mips/atheros/ar91xx_chip.c ============================================================================== --- head/sys/mips/atheros/ar91xx_chip.c Tue Oct 15 00:26:02 2013 (r256486) +++ head/sys/mips/atheros/ar91xx_chip.c Tue Oct 15 01:35:48 2013 (r256487) @@ -71,7 +71,7 @@ ar91xx_chip_detect_sys_frequency(void) uint32_t freq; uint32_t div; - u_ar71xx_refclk = AR91XX_BASE_FREQ; + u_ar71xx_mdio_freq = u_ar71xx_refclk = AR91XX_BASE_FREQ; pll = ATH_READ_REG(AR91XX_PLL_REG_CPU_CONFIG);