From owner-dev-commits-src-all@freebsd.org Fri Feb 19 22:25:23 2021 Return-Path: Delivered-To: dev-commits-src-all@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id E881B5423D5; Fri, 19 Feb 2021 22:25:22 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4Dj5kB2lLJz3h4x; Fri, 19 Feb 2021 22:25:22 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4F8961405F; Fri, 19 Feb 2021 22:25:22 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.16.1/8.16.1) with ESMTP id 11JMPMJb093533; Fri, 19 Feb 2021 22:25:22 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.16.1/8.16.1/Submit) id 11JMPMcM093532; Fri, 19 Feb 2021 22:25:22 GMT (envelope-from git) Date: Fri, 19 Feb 2021 22:25:22 GMT Message-Id: <202102192225.11JMPMcM093532@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Navdeep Parhar Subject: git: 0460a45062df - main - cxgbe(4): Use the correct filter width for T5+. MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: np X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 0460a45062dfeb98b1f1f7a3a7b9268662b61545 Auto-Submitted: auto-generated X-BeenThere: dev-commits-src-all@freebsd.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Commit messages for all branches of the src repository List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 19 Feb 2021 22:25:23 -0000 The branch main has been updated by np: URL: https://cgit.FreeBSD.org/src/commit/?id=0460a45062dfeb98b1f1f7a3a7b9268662b61545 commit 0460a45062dfeb98b1f1f7a3a7b9268662b61545 Author: Navdeep Parhar AuthorDate: 2021-02-19 22:18:08 +0000 Commit: Navdeep Parhar CommitDate: 2021-02-19 22:23:58 +0000 cxgbe(4): Use the correct filter width for T5+. T5 and above have extra bits for the optional filter fields. This is a correctness issue and not just a waste because a filter mode valid on a T4 (36b) may not be valid on a T5+ (40b). MFC after: 2 weeks Sponsored by: Chelsio Communications --- sys/dev/cxgbe/common/common.h | 1 + sys/dev/cxgbe/common/t4_hw.c | 5 ++++- sys/dev/cxgbe/common/t4_hw.h | 1 + 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/sys/dev/cxgbe/common/common.h b/sys/dev/cxgbe/common/common.h index 53be2fa2588a..e04101c9adc5 100644 --- a/sys/dev/cxgbe/common/common.h +++ b/sys/dev/cxgbe/common/common.h @@ -309,6 +309,7 @@ struct chip_params { u8 cng_ch_bits_log; /* congestion channel map bits width */ u8 nsched_cls; u8 cim_num_obq; + u8 filter_opt_len; u16 mps_rplc_size; u16 vfcount; u32 sge_fl_db; diff --git a/sys/dev/cxgbe/common/t4_hw.c b/sys/dev/cxgbe/common/t4_hw.c index 8b22f2e4f5ba..b3934381ba7a 100644 --- a/sys/dev/cxgbe/common/t4_hw.c +++ b/sys/dev/cxgbe/common/t4_hw.c @@ -9241,6 +9241,7 @@ const struct chip_params *t4_get_chip_params(int chipid) .cng_ch_bits_log = 2, .nsched_cls = 15, .cim_num_obq = CIM_NUM_OBQ, + .filter_opt_len = FILTER_OPT_LEN, .mps_rplc_size = 128, .vfcount = 128, .sge_fl_db = F_DBPRIO, @@ -9254,6 +9255,7 @@ const struct chip_params *t4_get_chip_params(int chipid) .cng_ch_bits_log = 2, .nsched_cls = 16, .cim_num_obq = CIM_NUM_OBQ_T5, + .filter_opt_len = T5_FILTER_OPT_LEN, .mps_rplc_size = 128, .vfcount = 128, .sge_fl_db = F_DBPRIO | F_DBTYPE, @@ -9267,6 +9269,7 @@ const struct chip_params *t4_get_chip_params(int chipid) .cng_ch_bits_log = 3, .nsched_cls = 16, .cim_num_obq = CIM_NUM_OBQ_T5, + .filter_opt_len = T5_FILTER_OPT_LEN, .mps_rplc_size = 256, .vfcount = 256, .sge_fl_db = 0, @@ -10863,7 +10866,7 @@ int t4_set_filter_cfg(struct adapter *adap, int mode, int mask, int vnic_mode) int i, nbits, rc; uint32_t param, val; uint16_t fmode, fmask; - const int maxbits = FILTER_OPT_LEN; + const int maxbits = adap->chip_params->filter_opt_len; if (mode != -1 || mask != -1) { if (mode != -1) { diff --git a/sys/dev/cxgbe/common/t4_hw.h b/sys/dev/cxgbe/common/t4_hw.h index 36ce6271dad6..c0625b752962 100644 --- a/sys/dev/cxgbe/common/t4_hw.h +++ b/sys/dev/cxgbe/common/t4_hw.h @@ -55,6 +55,7 @@ enum { NTRACE = 4, /* # of tracing filters */ TRACE_LEN = 112, /* length of trace data and mask */ FILTER_OPT_LEN = 36, /* filter tuple width of optional components */ + T5_FILTER_OPT_LEN = 40, NWOL_PAT = 8, /* # of WoL patterns */ WOL_PAT_LEN = 128, /* length of WoL patterns */ UDBS_SEG_SIZE = 128, /* Segment size of BAR2 doorbells */