Date: Tue, 28 Oct 97 18:56:54 -0800 From: "Mike Burgett" <mburgett@awen.com> To: "dg@root.com" <dg@root.com> Cc: "hackers@FreeBSD.ORG" <hackers@FreeBSD.ORG> Subject: Re: Parity Ram Message-ID: <199710290256.SAA18297@dragon.awen.com>
next in thread | raw e-mail | index | archive | help
On Tue, 28 Oct 1997 17:29:28 -0800, David Greenman wrote: >In order to update the memory, the ECC must be recalculated over >the entire 64bit quadword. This escentially means that you have to read >the memory first, apply the changes/calculate the new ECC and then write >it back. Obviously, this makes memory writes quite a bit slower. Ummm. Hmmmm. Doesn't the memory subsystem interact with the L2 cache on a per-line basis anyway? IOW, a cache line is read in anytime a byte is accessed, and when it's time to write, the line is either dirty, or it isn't, and if it is, the whole thing is burst back to memory anyway... I thought the (slight) performance penalty was to allow a clock or two for the new ECC to be calculated, not because a write occurred. Then again, maybe it's just me. :) (Or maybe the PC is different from other hardware I've been more intimate with...) --Mike
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?199710290256.SAA18297>