Date: Mon, 22 Mar 2010 23:31:48 +0000 (UTC) From: Juli Mallett <jmallett@FreeBSD.org> To: src-committers@freebsd.org, svn-src-user@freebsd.org Subject: svn commit: r205492 - in user/jmallett/octeon/sys/mips: include mips Message-ID: <201003222331.o2MNVmQS073258@svn.freebsd.org>
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Author: jmallett Date: Mon Mar 22 23:31:48 2010 New Revision: 205492 URL: http://svn.freebsd.org/changeset/base/205492 Log: An unfortunate mix of functional and stylistic changes. o) Use REG_{S,L} and PTR_{S,L,LA} in support.S and use width-specific instructions only where reasonable. o) Consistently use CALLFRAME_SIZ for callframe size, rather than using the mysterious STAND_ frame. o) Remove a stray ".set mips2" which would screw up instructions used by setjmp and longjmp quite astonishingly. o) Get rid of some home-grown STORE/LOAD and replace with REG_S/REG_L in a few files. o) Make pcb_onfault a pointer, the address of the function to be called, rather than using the onfault_table -- the latter being especially wrongly-used by casuptr at minimum. XXX This did require one gross hack of a slightly-less-gross nature than the one used prior to it wrt [sf].*intr functions. o) Fix compilation of TRAP_DEBUG and make a point of using intmax_t rather than trying to decide between truncating and extending addresses on a case-by-case basis when printing stuff in trap.c o) Don't NULL out pcb_onfault in the actual onfault handlers, the trap handler makes a point of doing that. Sponsored by: Packet Forensics Modified: user/jmallett/octeon/sys/mips/include/pcb.h user/jmallett/octeon/sys/mips/include/regnum.h user/jmallett/octeon/sys/mips/mips/exception.S user/jmallett/octeon/sys/mips/mips/fp.S user/jmallett/octeon/sys/mips/mips/support.S user/jmallett/octeon/sys/mips/mips/swtch.S user/jmallett/octeon/sys/mips/mips/trap.c user/jmallett/octeon/sys/mips/mips/vm_machdep.c Modified: user/jmallett/octeon/sys/mips/include/pcb.h ============================================================================== --- user/jmallett/octeon/sys/mips/include/pcb.h Mon Mar 22 23:27:08 2010 (r205491) +++ user/jmallett/octeon/sys/mips/include/pcb.h Mon Mar 22 23:31:48 2010 (r205492) @@ -51,7 +51,7 @@ struct pcb { struct trapframe pcb_regs; /* saved CPU and registers */ __register_t pcb_context[14]; /* kernel context for resume */ - int pcb_onfault; /* for copyin/copyout faults */ + void *pcb_onfault; /* for copyin/copyout faults */ register_t pcb_tpc; }; Modified: user/jmallett/octeon/sys/mips/include/regnum.h ============================================================================== --- user/jmallett/octeon/sys/mips/include/regnum.h Mon Mar 22 23:27:08 2010 (r205491) +++ user/jmallett/octeon/sys/mips/include/regnum.h Mon Mar 22 23:31:48 2010 (r205492) @@ -42,10 +42,6 @@ #ifndef _MACHINE_REGNUM_H_ #define _MACHINE_REGNUM_H_ -#define STAND_ARG_SIZE 16 -#define STAND_FRAME_SIZE 24 -#define STAND_RA_OFFSET 20 - /* This must match the numbers * in pcb.h and is used by * swtch.S Modified: user/jmallett/octeon/sys/mips/mips/exception.S ============================================================================== --- user/jmallett/octeon/sys/mips/mips/exception.S Mon Mar 22 23:27:08 2010 (r205491) +++ user/jmallett/octeon/sys/mips/mips/exception.S Mon Mar 22 23:31:48 2010 (r205492) @@ -244,20 +244,9 @@ SlowFault: * *---------------------------------------------------------------------------- */ -#if defined(ISA_MIPS32) -#define STORE sw /* 32 bit mode regsave instruction */ -#define LOAD lw /* 32 bit mode regload instruction */ -#define RSIZE 4 /* 32 bit mode register size */ -#elif defined(ISA_MIPS64) -#define STORE sd /* 64 bit mode regsave instruction */ -#define LOAD ld /* 64 bit mode regload instruction */ -#define RSIZE 8 /* 64 bit mode register size */ -#else -#error "Please write code for this isa." -#endif #define SAVE_REG(reg, offs, base) \ - STORE reg, STAND_ARG_SIZE + (RSIZE * offs) (base) + REG_S reg, CALLFRAME_SIZ + (SZREG * offs) (base) #ifdef TARGET_OCTEON #define CLEAR_STATUS \ @@ -332,11 +321,11 @@ SlowFault: PTR_ADDU v0, sp, KERN_EXC_FRAME_SIZE ;\ SAVE_REG(v0, SP, sp) ;\ CLEAR_STATUS ;\ - PTR_ADDU a0, sp, STAND_ARG_SIZE ;\ + PTR_ADDU a0, sp, CALLFRAME_SIZ ;\ ITLBNOPFIX #define RESTORE_REG(reg, offs, base) \ - LOAD reg, STAND_ARG_SIZE + (RSIZE * offs) (base) + REG_L reg, CALLFRAME_SIZ + (SZREG * offs) (base) #define RESTORE_CPU \ mtc0 zero,COP_0_STATUS_REG ;\ @@ -384,13 +373,13 @@ SlowFault: * the status register and the multiply lo and high registers. * In addition, we set this up for linkage conventions. */ -#define KERN_REG_SIZE (NUMSAVEREGS * RSIZE) -#define KERN_EXC_FRAME_SIZE (STAND_FRAME_SIZE + KERN_REG_SIZE + 16) +#define KERN_REG_SIZE (NUMSAVEREGS * SZREG) +#define KERN_EXC_FRAME_SIZE (CALLFRAME_SIZ + KERN_REG_SIZE + 16) NNON_LEAF(MipsKernGenException, KERN_EXC_FRAME_SIZE, ra) .set noat subu sp, sp, KERN_EXC_FRAME_SIZE - .mask 0x80000000, (STAND_RA_OFFSET - KERN_EXC_FRAME_SIZE) + .mask 0x80000000, (CALLFRAME_RA - KERN_EXC_FRAME_SIZE) /* * Save CPU state, building 'frame'. */ @@ -401,7 +390,7 @@ NNON_LEAF(MipsKernGenException, KERN_EXC PTR_LA gp, _C_LABEL(_gp) PTR_LA k0, _C_LABEL(trap) jalr k0 - sw a3, STAND_RA_OFFSET + KERN_REG_SIZE(sp) # for debugging + sw a3, CALLFRAME_RA + KERN_REG_SIZE(sp) # for debugging /* * Update interrupt mask in saved status register @@ -424,10 +413,10 @@ END(MipsKernGenException) #define SAVE_U_PCB_REG(reg, offs, base) \ - STORE reg, U_PCB_REGS + (RSIZE * offs) (base) + REG_S reg, U_PCB_REGS + (SZREG * offs) (base) #define RESTORE_U_PCB_REG(reg, offs, base) \ - LOAD reg, U_PCB_REGS + (RSIZE * offs) (base) + REG_L reg, U_PCB_REGS + (SZREG * offs) (base) /*---------------------------------------------------------------------------- * @@ -443,9 +432,9 @@ END(MipsKernGenException) * *---------------------------------------------------------------------------- */ -NNON_LEAF(MipsUserGenException, STAND_FRAME_SIZE, ra) +NNON_LEAF(MipsUserGenException, CALLFRAME_SIZ, ra) .set noat - .mask 0x80000000, (STAND_RA_OFFSET - STAND_FRAME_SIZE) + .mask 0x80000000, (CALLFRAME_RA - CALLFRAME_SIZ) /* * Save all of the registers except for the kernel temporaries in u.u_pcb. */ @@ -486,7 +475,7 @@ NNON_LEAF(MipsUserGenException, STAND_FR SAVE_U_PCB_REG(gp, GP, k1) SAVE_U_PCB_REG(sp, SP, k1) SAVE_U_PCB_REG(s8, S8, k1) - subu sp, k1, STAND_FRAME_SIZE # switch to kernel SP + subu sp, k1, CALLFRAME_SIZ # switch to kernel SP SAVE_U_PCB_REG(ra, RA, k1) SAVE_U_PCB_REG(v0, MULLO, k1) SAVE_U_PCB_REG(v1, MULHI, k1) @@ -494,7 +483,7 @@ NNON_LEAF(MipsUserGenException, STAND_FR SAVE_U_PCB_REG(a1, CAUSE, k1) SAVE_U_PCB_REG(a2, BADVADDR, k1) SAVE_U_PCB_REG(a3, PC, k1) - sw a3, STAND_RA_OFFSET(sp) # for debugging + sw a3, CALLFRAME_RA(sp) # for debugging PTR_LA gp, _C_LABEL(_gp) # switch to kernel GP # Turn off fpu and enter kernel mode and t0, a0, ~(SR_COP_1_BIT | SR_EXL | SR_KSU_MASK | SR_INT_ENAB) @@ -611,7 +600,7 @@ END(MipsUserGenException) NNON_LEAF(MipsKernIntr, KERN_EXC_FRAME_SIZE, ra) .set noat subu sp, sp, KERN_EXC_FRAME_SIZE - .mask 0x80000000, (STAND_RA_OFFSET - KERN_EXC_FRAME_SIZE) + .mask 0x80000000, (CALLFRAME_RA - KERN_EXC_FRAME_SIZE) /* * Save the relevant kernel registers onto the stack. */ @@ -621,10 +610,10 @@ NNON_LEAF(MipsKernIntr, KERN_EXC_FRAME_S * Call the interrupt handler. */ PTR_LA gp, _C_LABEL(_gp) - PTR_ADDU a0, sp, STAND_ARG_SIZE + PTR_ADDU a0, sp, CALLFRAME_SIZ PTR_LA k0, _C_LABEL(cpu_intr) jalr k0 - sw a3, STAND_RA_OFFSET + KERN_REG_SIZE(sp) + sw a3, CALLFRAME_RA + KERN_REG_SIZE(sp) /* Why no AST processing here? */ /* @@ -642,7 +631,7 @@ NNON_LEAF(MipsKernIntr, KERN_EXC_FRAME_S /* * Restore registers and return from the interrupt. */ - lw v0, STAND_RA_OFFSET + KERN_REG_SIZE(sp) + lw v0, CALLFRAME_RA + KERN_REG_SIZE(sp) RESTORE_CPU sync eret @@ -668,9 +657,9 @@ END(MipsKernIntr) * *---------------------------------------------------------------------------- */ -NNON_LEAF(MipsUserIntr, STAND_FRAME_SIZE, ra) +NNON_LEAF(MipsUserIntr, CALLFRAME_SIZ, ra) .set noat - .mask 0x80000000, (STAND_RA_OFFSET - STAND_FRAME_SIZE) + .mask 0x80000000, (CALLFRAME_RA - CALLFRAME_SIZ) /* * Save the relevant user registers into the u.u_pcb struct. * We don't need to save s0 - s8 because the compiler does it for us. @@ -721,7 +710,7 @@ NNON_LEAF(MipsUserIntr, STAND_FRAME_SIZE SAVE_U_PCB_REG(a0, SR, k1) SAVE_U_PCB_REG(a1, CAUSE, k1) SAVE_U_PCB_REG(a3, PC, k1) # PC in a3, note used later! - subu sp, k1, STAND_FRAME_SIZE # switch to kernel SP + subu sp, k1, CALLFRAME_SIZ # switch to kernel SP PTR_LA gp, _C_LABEL(_gp) # switch to kernel GP # Turn off fpu, disable interrupts, set kernel mode kernel mode, clear exception level. @@ -737,7 +726,7 @@ NNON_LEAF(MipsUserIntr, STAND_FRAME_SIZE */ PTR_LA k0, _C_LABEL(cpu_intr) jalr k0 - sw a3, STAND_RA_OFFSET(sp) # for debugging + sw a3, CALLFRAME_RA(sp) # for debugging /* * Enable interrupts before doing ast(). @@ -1132,11 +1121,11 @@ END(MipsTLBMissException) * *---------------------------------------------------------------------------- */ -NON_LEAF(MipsFPTrap, STAND_FRAME_SIZE, ra) - subu sp, sp, STAND_FRAME_SIZE +NON_LEAF(MipsFPTrap, CALLFRAME_SIZ, ra) + subu sp, sp, CALLFRAME_SIZ mfc0 t0, COP_0_STATUS_REG - sw ra, STAND_RA_OFFSET(sp) - .mask 0x80000000, (STAND_RA_OFFSET - STAND_FRAME_SIZE) + sw ra, CALLFRAME_RA(sp) + .mask 0x80000000, (CALLFRAME_RA - CALLFRAME_SIZ) or t1, t0, SR_COP_1_BIT mtc0 t1, COP_0_STATUS_REG @@ -1157,7 +1146,7 @@ NON_LEAF(MipsFPTrap, STAND_FRAME_SIZE, r * The instruction is in the branch delay slot so the branch will have to * be emulated to get the resulting PC. */ - sw a2, STAND_FRAME_SIZE + 8(sp) + sw a2, CALLFRAME_SIZ + 8(sp) GET_CPU_PCPU(a0) #mips64 unsafe? lw a0, PC_CURPCB(a0) @@ -1171,7 +1160,7 @@ NON_LEAF(MipsFPTrap, STAND_FRAME_SIZE, r * Now load the floating-point instruction in the branch delay slot * to be emulated. */ - lw a2, STAND_FRAME_SIZE + 8(sp) # restore EXC pc + lw a2, CALLFRAME_SIZ + 8(sp) # restore EXC pc b 2f lw a0, 4(a2) # a0 = coproc instruction /* @@ -1220,12 +1209,12 @@ NON_LEAF(MipsFPTrap, STAND_FRAME_SIZE, r */ FPReturn: mfc0 t0, COP_0_STATUS_REG - lw ra, STAND_RA_OFFSET(sp) + lw ra, CALLFRAME_RA(sp) and t0, t0, ~SR_COP_1_BIT mtc0 t0, COP_0_STATUS_REG ITLBNOPFIX j ra - PTR_ADDU sp, sp, STAND_FRAME_SIZE + PTR_ADDU sp, sp, CALLFRAME_SIZ END(MipsFPTrap) /* Modified: user/jmallett/octeon/sys/mips/mips/fp.S ============================================================================== --- user/jmallett/octeon/sys/mips/mips/fp.S Mon Mar 22 23:27:08 2010 (r205491) +++ user/jmallett/octeon/sys/mips/mips/fp.S Mon Mar 22 23:31:48 2010 (r205492) @@ -94,9 +94,9 @@ * *---------------------------------------------------------------------------- */ -NON_LEAF(MipsEmulateFP, STAND_FRAME_SIZE, ra) - subu sp, sp, STAND_FRAME_SIZE - sw ra, STAND_RA_OFFSET(sp) +NON_LEAF(MipsEmulateFP, CALLFRAME_SIZ, ra) + subu sp, sp, CALLFRAME_SIZ + sw ra, CALLFRAME_RA(sp) /* * Decode the FMT field (bits 24-21) and FUNCTION field (bits 5-0). */ @@ -2247,8 +2247,8 @@ result_fs_d: # result is FS jal set_fd_d # save result (in t0,t1,t2,t3) done: - lw ra, STAND_RA_OFFSET(sp) - addu sp, sp, STAND_FRAME_SIZE + lw ra, CALLFRAME_RA(sp) + addu sp, sp, CALLFRAME_SIZ j ra END(MipsEmulateFP) Modified: user/jmallett/octeon/sys/mips/mips/support.S ============================================================================== --- user/jmallett/octeon/sys/mips/mips/support.S Mon Mar 22 23:27:08 2010 (r205491) +++ user/jmallett/octeon/sys/mips/mips/support.S Mon Mar 22 23:31:48 2010 (r205492) @@ -70,47 +70,22 @@ * Primitives */ -/* - * This table is indexed by u.u_pcb.pcb_onfault in trap(). - * The reason for using this table rather than storing an address in - * u.u_pcb.pcb_onfault is simply to make the code faster. - */ - .globl onfault_table - .data - .align 3 -onfault_table: - .word 0 # invalid index number -#define BADERR 1 - .word baderr -#define COPYERR 2 - .word copyerr -#define FSWBERR 3 - .word fswberr -#define FSWINTRBERR 4 - .word fswintrberr -#if defined(DDB) || defined(DEBUG) -#define DDBERR 5 - .word ddberr -#else - .word 0 -#endif - .text /* * See if access to addr with a len type instruction causes a machine check. - * len is length of access (1=byte, 2=short, 4=long) + * len is length of access (1=byte, 2=short, 4=int) * * badaddr(addr, len) * char *addr; * int len; */ LEAF(badaddr) - li v0, BADERR + PTR_LA v0, baderr GET_CPU_PCPU(v1) - lw v1, PC_CURPCB(v1) + PTR_L v1, PC_CURPCB(v1) bne a1, 1, 2f - sw v0, U_PCB_ONFAULT(v1) + PTR_S v0, U_PCB_ONFAULT(v1) b 5f lbu v0, (a0) 2: @@ -121,7 +96,7 @@ LEAF(badaddr) 4: lw v0, (a0) 5: - sw zero, U_PCB_ONFAULT(v1) + PTR_S zero, U_PCB_ONFAULT(v1) j ra move v0, zero # made it w/o errors baderr: @@ -310,22 +285,22 @@ END(outsl) * u_int maxlength; * u_int *lencopied; */ -NON_LEAF(copyinstr, STAND_FRAME_SIZE, ra) - subu sp, sp, STAND_FRAME_SIZE - .mask 0x80000000, (STAND_RA_OFFSET - STAND_FRAME_SIZE) - sw ra, STAND_RA_OFFSET(sp) +NON_LEAF(copyinstr, CALLFRAME_SIZ, ra) + PTR_SUBU sp, sp, CALLFRAME_SIZ + .mask 0x80000000, (CALLFRAME_RA - CALLFRAME_SIZ) + PTR_LA v0, copyerr blt a0, zero, _C_LABEL(copyerr) # make sure address is in user space - li v0, COPYERR + REG_S ra, CALLFRAME_RA(sp) GET_CPU_PCPU(v1) - lw v1, PC_CURPCB(v1) + PTR_L v1, PC_CURPCB(v1) jal _C_LABEL(copystr) - sw v0, U_PCB_ONFAULT(v1) - lw ra, STAND_RA_OFFSET(sp) + PTR_S v0, U_PCB_ONFAULT(v1) + REG_L ra, CALLFRAME_RA(sp) GET_CPU_PCPU(v1) - lw v1, PC_CURPCB(v1) - sw zero, U_PCB_ONFAULT(v1) + PTR_L v1, PC_CURPCB(v1) + PTR_S zero, U_PCB_ONFAULT(v1) j ra - addu sp, sp, STAND_FRAME_SIZE + PTR_ADDU sp, sp, CALLFRAME_SIZ END(copyinstr) /* @@ -338,22 +313,22 @@ END(copyinstr) * u_int maxlength; * u_int *lencopied; */ -NON_LEAF(copyoutstr, STAND_FRAME_SIZE, ra) - subu sp, sp, STAND_FRAME_SIZE - .mask 0x80000000, (STAND_RA_OFFSET - STAND_FRAME_SIZE) - sw ra, STAND_RA_OFFSET(sp) +NON_LEAF(copyoutstr, CALLFRAME_SIZ, ra) + PTR_SUBU sp, sp, CALLFRAME_SIZ + .mask 0x80000000, (CALLFRAME_RA - CALLFRAME_SIZ) + PTR_LA v0, copyerr blt a1, zero, _C_LABEL(copyerr) # make sure address is in user space - li v0, COPYERR + REG_S ra, CALLFRAME_RA(sp) GET_CPU_PCPU(v1) - lw v1, PC_CURPCB(v1) + PTR_L v1, PC_CURPCB(v1) jal _C_LABEL(copystr) - sw v0, U_PCB_ONFAULT(v1) - lw ra, STAND_RA_OFFSET(sp) + PTR_S v0, U_PCB_ONFAULT(v1) + REG_L ra, CALLFRAME_RA(sp) GET_CPU_PCPU(v1) - lw v1, PC_CURPCB(v1) - sw zero, U_PCB_ONFAULT(v1) + PTR_L v1, PC_CURPCB(v1) + PTR_S zero, U_PCB_ONFAULT(v1) j ra - addu sp, sp, STAND_FRAME_SIZE + PTR_ADDU sp, sp, CALLFRAME_SIZ END(copyoutstr) /* @@ -363,21 +338,21 @@ END(copyoutstr) * caddr_t *to; (kernel destination address) * unsigned len; */ -NON_LEAF(copyin, STAND_FRAME_SIZE, ra) - subu sp, sp, STAND_FRAME_SIZE - .mask 0x80000000, (STAND_RA_OFFSET - STAND_FRAME_SIZE) - sw ra, STAND_RA_OFFSET(sp) +NON_LEAF(copyin, CALLFRAME_SIZ, ra) + PTR_SUBU sp, sp, CALLFRAME_SIZ + .mask 0x80000000, (CALLFRAME_RA - CALLFRAME_SIZ) + PTR_LA v0, copyerr blt a0, zero, _C_LABEL(copyerr) # make sure address is in user space - li v0, COPYERR + REG_S ra, CALLFRAME_RA(sp) GET_CPU_PCPU(v1) - lw v1, PC_CURPCB(v1) + PTR_L v1, PC_CURPCB(v1) jal _C_LABEL(bcopy) - sw v0, U_PCB_ONFAULT(v1) - lw ra, STAND_RA_OFFSET(sp) + PTR_S v0, U_PCB_ONFAULT(v1) + REG_L ra, CALLFRAME_RA(sp) GET_CPU_PCPU(v1) - lw v1, PC_CURPCB(v1) # bcopy modified v1, so reload - sw zero, U_PCB_ONFAULT(v1) - addu sp, sp, STAND_FRAME_SIZE + PTR_L v1, PC_CURPCB(v1) # bcopy modified v1, so reload + PTR_S zero, U_PCB_ONFAULT(v1) + PTR_ADDU sp, sp, CALLFRAME_SIZ j ra move v0, zero END(copyin) @@ -389,31 +364,28 @@ END(copyin) * caddr_t *to; (user destination address) * unsigned len; */ -NON_LEAF(copyout, STAND_FRAME_SIZE, ra) - subu sp, sp, STAND_FRAME_SIZE - .mask 0x80000000, (STAND_RA_OFFSET - STAND_FRAME_SIZE) - sw ra, STAND_RA_OFFSET(sp) +NON_LEAF(copyout, CALLFRAME_SIZ, ra) + PTR_SUBU sp, sp, CALLFRAME_SIZ + .mask 0x80000000, (CALLFRAME_RA - CALLFRAME_SIZ) + PTR_LA v0, copyerr blt a1, zero, _C_LABEL(copyerr) # make sure address is in user space - li v0, COPYERR + REG_S ra, CALLFRAME_RA(sp) GET_CPU_PCPU(v1) - lw v1, PC_CURPCB(v1) + PTR_L v1, PC_CURPCB(v1) jal _C_LABEL(bcopy) - sw v0, U_PCB_ONFAULT(v1) - lw ra, STAND_RA_OFFSET(sp) + PTR_S v0, U_PCB_ONFAULT(v1) + REG_L ra, CALLFRAME_RA(sp) GET_CPU_PCPU(v1) - lw v1, PC_CURPCB(v1) # bcopy modified v1, so reload - sw zero, U_PCB_ONFAULT(v1) - addu sp, sp, STAND_FRAME_SIZE + PTR_L v1, PC_CURPCB(v1) # bcopy modified v1, so reload + PTR_S zero, U_PCB_ONFAULT(v1) + PTR_ADDU sp, sp, CALLFRAME_SIZ j ra move v0, zero END(copyout) LEAF(copyerr) - lw ra, STAND_RA_OFFSET(sp) - GET_CPU_PCPU(v1) - lw v1, PC_CURPCB(v1) - sw zero, U_PCB_ONFAULT(v1) - addu sp, sp, STAND_FRAME_SIZE + REG_L ra, CALLFRAME_RA(sp) + PTR_ADDU sp, sp, CALLFRAME_SIZ j ra li v0, EFAULT # return error END(copyerr) @@ -427,51 +399,55 @@ END(copyerr) LEAF(fuword) ALEAF(fuword32) ALEAF(fuiword) + PTR_LA v0, fswberr blt a0, zero, fswberr # make sure address is in user space - li v0, FSWBERR + nop GET_CPU_PCPU(v1) - lw v1, PC_CURPCB(v1) - sw v0, U_PCB_ONFAULT(v1) + PTR_L v1, PC_CURPCB(v1) + PTR_S v0, U_PCB_ONFAULT(v1) lw v0, 0(a0) # fetch word j ra - sw zero, U_PCB_ONFAULT(v1) + PTR_S zero, U_PCB_ONFAULT(v1) END(fuword) LEAF(fusword) ALEAF(fuisword) + PTR_LA v0, fswberr blt a0, zero, fswberr # make sure address is in user space - li v0, FSWBERR + nop GET_CPU_PCPU(v1) - lw v1, PC_CURPCB(v1) - sw v0, U_PCB_ONFAULT(v1) + PTR_L v1, PC_CURPCB(v1) + PTR_S v0, U_PCB_ONFAULT(v1) lhu v0, 0(a0) # fetch short j ra - sw zero, U_PCB_ONFAULT(v1) + PTR_S zero, U_PCB_ONFAULT(v1) END(fusword) LEAF(fubyte) ALEAF(fuibyte) + PTR_LA v0, fswberr blt a0, zero, fswberr # make sure address is in user space - li v0, FSWBERR + nop GET_CPU_PCPU(v1) - lw v1, PC_CURPCB(v1) - sw v0, U_PCB_ONFAULT(v1) + PTR_L v1, PC_CURPCB(v1) + PTR_S v0, U_PCB_ONFAULT(v1) lbu v0, 0(a0) # fetch byte j ra - sw zero, U_PCB_ONFAULT(v1) + PTR_S zero, U_PCB_ONFAULT(v1) END(fubyte) LEAF(suword32) #ifndef __mips_n64 XLEAF(suword) #endif + PTR_LA v0, fswberr blt a0, zero, fswberr # make sure address is in user space - li v0, FSWBERR + nop GET_CPU_PCPU(v1) - lw v1, PC_CURPCB(v1) - sw v0, U_PCB_ONFAULT(v1) + PTR_L v1, PC_CURPCB(v1) + PTR_S v0, U_PCB_ONFAULT(v1) sw a1, 0(a0) # store word - sw zero, U_PCB_ONFAULT(v1) + PTR_S zero, U_PCB_ONFAULT(v1) j ra move v0, zero END(suword32) @@ -479,13 +455,14 @@ END(suword32) #ifdef __mips_n64 LEAF(suword64) XLEAF(suword) + PTR_LA v0, fswberr blt a0, zero, fswberr # make sure address is in user space - li v0, FSWBERR + nop GET_CPU_PCPU(v1) - lw v1, PC_CURPCB(v1) - sw v0, U_PCB_ONFAULT(v1) + PTR_L v1, PC_CURPCB(v1) + PTR_S v0, U_PCB_ONFAULT(v1) sd a1, 0(a0) # store word - sw zero, U_PCB_ONFAULT(v1) + PTR_S zero, U_PCB_ONFAULT(v1) j ra move v0, zero END(suword64) @@ -504,11 +481,12 @@ LEAF(casuword32) #ifndef __mips_n64 XLEAF(casuword) #endif + PTR_LA v0, fswberr blt a0, zero, fswberr # make sure address is in user space - li v0, FSWBERR + nop GET_CPU_PCPU(v1) - lw v1, PC_CURPCB(v1) - sw v0, U_PCB_ONFAULT(v1) + PTR_L v1, PC_CURPCB(v1) + PTR_S v0, U_PCB_ONFAULT(v1) 1: move t0, a2 ll v0, 0(a0) @@ -522,7 +500,7 @@ XLEAF(casuword) 2: li v0, -1 3: - sw zero, U_PCB_ONFAULT(v1) + PTR_S zero, U_PCB_ONFAULT(v1) jr ra nop END(casuword32) @@ -530,11 +508,12 @@ END(casuword32) #ifdef __mips_n64 LEAF(casuword64) XLEAF(casuword) + PTR_LA v0, fswberr blt a0, zero, fswberr # make sure address is in user space - li v0, FSWBERR + nop GET_CPU_PCPU(v1) - lw v1, PC_CURPCB(v1) - sw v0, U_PCB_ONFAULT(v1) + PTR_L v1, PC_CURPCB(v1) + PTR_S v0, U_PCB_ONFAULT(v1) 1: move t0, a2 lld v0, 0(a0) @@ -548,7 +527,7 @@ XLEAF(casuword) 2: li v0, -1 3: - sw zero, U_PCB_ONFAULT(v1) + PTR_S zero, U_PCB_ONFAULT(v1) jr ra nop END(casuword64) @@ -560,13 +539,14 @@ END(casuword64) * Have to flush instruction cache afterwards. */ LEAF(suiword) + PTR_LA v0, fswberr blt a0, zero, fswberr # make sure address is in user space - li v0, FSWBERR + nop GET_CPU_PCPU(v1) - lw v1, PC_CURPCB(v1) - sw v0, U_PCB_ONFAULT(v1) + PTR_L v1, PC_CURPCB(v1) + PTR_S v0, U_PCB_ONFAULT(v1) sw a1, 0(a0) # store word - sw zero, U_PCB_ONFAULT(v1) + PTR_S zero, U_PCB_ONFAULT(v1) j _C_LABEL(Mips_SyncICache) # FlushICache sets v0 = 0. (Ugly) li a1, 4 # size of word END(suiword) @@ -577,26 +557,28 @@ END(suiword) */ LEAF(susword) ALEAF(suisword) + PTR_LA v0, fswberr blt a0, zero, fswberr # make sure address is in user space - li v0, FSWBERR + nop GET_CPU_PCPU(v1) - lw v1, PC_CURPCB(v1) - sw v0, U_PCB_ONFAULT(v1) + PTR_L v1, PC_CURPCB(v1) + PTR_S v0, U_PCB_ONFAULT(v1) sh a1, 0(a0) # store short - sw zero, U_PCB_ONFAULT(v1) + PTR_S zero, U_PCB_ONFAULT(v1) j ra move v0, zero END(susword) LEAF(subyte) ALEAF(suibyte) + PTR_LA v0, fswberr blt a0, zero, fswberr # make sure address is in user space - li v0, FSWBERR + nop GET_CPU_PCPU(v1) - lw v1, PC_CURPCB(v1) - sw v0, U_PCB_ONFAULT(v1) + PTR_L v1, PC_CURPCB(v1) + PTR_S v0, U_PCB_ONFAULT(v1) sb a1, 0(a0) # store byte - sw zero, U_PCB_ONFAULT(v1) + PTR_S zero, U_PCB_ONFAULT(v1) j ra move v0, zero END(subyte) @@ -612,24 +594,26 @@ END(fswberr) * The important thing is to prevent sleep() and switch(). */ LEAF(fuswintr) + PTR_LA v0, fswintrberr blt a0, zero, fswintrberr # make sure address is in user space - li v0, FSWINTRBERR + nop GET_CPU_PCPU(v1) - lw v1, PC_CURPCB(v1) - sw v0, U_PCB_ONFAULT(v1) + PTR_L v1, PC_CURPCB(v1) + PTR_S v0, U_PCB_ONFAULT(v1) lhu v0, 0(a0) # fetch short j ra - sw zero, U_PCB_ONFAULT(v1) + PTR_S zero, U_PCB_ONFAULT(v1) END(fuswintr) LEAF(suswintr) + PTR_LA v0, fswintrberr blt a0, zero, fswintrberr # make sure address is in user space - li v0, FSWINTRBERR + nop GET_CPU_PCPU(v1) - lw v1, PC_CURPCB(v1) - sw v0, U_PCB_ONFAULT(v1) + PTR_L v1, PC_CURPCB(v1) + PTR_S v0, U_PCB_ONFAULT(v1) sh a1, 0(a0) # store short - sw zero, U_PCB_ONFAULT(v1) + PTR_S zero, U_PCB_ONFAULT(v1) j ra move v0, zero END(suswintr) @@ -1393,22 +1377,22 @@ END(atomic_load_64) #if defined(DDB) || defined(DEBUG) LEAF(kdbpeek) - li v1, DDBERR + PTR_LA v1, ddberr and v0, a0, 3 # unaligned ? GET_CPU_PCPU(t1) - lw t1, PC_CURPCB(t1) + PTR_L t1, PC_CURPCB(t1) bne v0, zero, 1f - sw v1, U_PCB_ONFAULT(t1) + PTR_S v1, U_PCB_ONFAULT(t1) lw v0, (a0) jr ra - sw zero, U_PCB_ONFAULT(t1) + PTR_S zero, U_PCB_ONFAULT(t1) 1: LWHI v0, 0(a0) LWLO v0, 3(a0) jr ra - sw zero, U_PCB_ONFAULT(t1) + PTR_S zero, U_PCB_ONFAULT(t1) END(kdbpeek) ddberr: @@ -1417,44 +1401,31 @@ ddberr: #if defined(DDB) LEAF(kdbpoke) - li v1, DDBERR + PTR_LA v1, ddberr and v0, a0, 3 # unaligned ? GET_CPU_PCPU(t1) - lw t1, PC_CURPCB(t1) + PTR_L t1, PC_CURPCB(t1) bne v0, zero, 1f - sw v1, U_PCB_ONFAULT(t1) + PTR_S v1, U_PCB_ONFAULT(t1) sw a1, (a0) jr ra - sw zero, U_PCB_ONFAULT(t1) + PTR_S zero, U_PCB_ONFAULT(t1) 1: SWHI a1, 0(a0) SWLO a1, 3(a0) jr ra - sw zero, U_PCB_ONFAULT(t1) + PTR_S zero, U_PCB_ONFAULT(t1) END(kdbpoke) .data .globl esym esym: .word 0 -#ifndef _MIPS_ARCH_XLR - .set mips2 -#endif #endif /* DDB */ #endif /* DDB || DEBUG */ -#ifndef MIPS_ISAIII -#define STORE sw /* 32 bit mode regsave instruction */ -#define LOAD lw /* 32 bit mode regload instruction */ -#define RSIZE 4 /* 32 bit mode register size */ -#else -#define STORE sd /* 64 bit mode regsave instruction */ -#define LOAD ld /* 64 bit mode regload instruction */ -#define RSIZE 8 /* 64 bit mode register size */ -#endif - #define ITLBNOPFIX nop;nop;nop;nop;nop;nop;nop;nop;nop;nop; .text @@ -1466,35 +1437,35 @@ LEAF(breakpoint) LEAF(setjmp) mfc0 v0, COP_0_STATUS_REG # Later the "real" spl value! - STORE s0, (RSIZE * PREG_S0)(a0) - STORE s1, (RSIZE * PREG_S1)(a0) - STORE s2, (RSIZE * PREG_S2)(a0) - STORE s3, (RSIZE * PREG_S3)(a0) - STORE s4, (RSIZE * PREG_S4)(a0) - STORE s5, (RSIZE * PREG_S5)(a0) - STORE s6, (RSIZE * PREG_S6)(a0) - STORE s7, (RSIZE * PREG_S7)(a0) - STORE s8, (RSIZE * PREG_S8)(a0) - STORE sp, (RSIZE * PREG_SP)(a0) - STORE ra, (RSIZE * PREG_RA)(a0) - STORE v0, (RSIZE * PREG_SR)(a0) + REG_S s0, (SZREG * PREG_S0)(a0) + REG_S s1, (SZREG * PREG_S1)(a0) + REG_S s2, (SZREG * PREG_S2)(a0) + REG_S s3, (SZREG * PREG_S3)(a0) + REG_S s4, (SZREG * PREG_S4)(a0) + REG_S s5, (SZREG * PREG_S5)(a0) + REG_S s6, (SZREG * PREG_S6)(a0) + REG_S s7, (SZREG * PREG_S7)(a0) + REG_S s8, (SZREG * PREG_S8)(a0) + REG_S sp, (SZREG * PREG_SP)(a0) + REG_S ra, (SZREG * PREG_RA)(a0) + REG_S v0, (SZREG * PREG_SR)(a0) jr ra li v0, 0 # setjmp return END(setjmp) LEAF(longjmp) - LOAD v0, (RSIZE * PREG_SR)(a0) - LOAD ra, (RSIZE * PREG_RA)(a0) - LOAD s0, (RSIZE * PREG_S0)(a0) - LOAD s1, (RSIZE * PREG_S1)(a0) - LOAD s2, (RSIZE * PREG_S2)(a0) - LOAD s3, (RSIZE * PREG_S3)(a0) - LOAD s4, (RSIZE * PREG_S4)(a0) - LOAD s5, (RSIZE * PREG_S5)(a0) - LOAD s6, (RSIZE * PREG_S6)(a0) - LOAD s7, (RSIZE * PREG_S7)(a0) - LOAD s8, (RSIZE * PREG_S8)(a0) - LOAD sp, (RSIZE * PREG_SP)(a0) + REG_L v0, (SZREG * PREG_SR)(a0) + REG_L ra, (SZREG * PREG_RA)(a0) + REG_L s0, (SZREG * PREG_S0)(a0) + REG_L s1, (SZREG * PREG_S1)(a0) + REG_L s2, (SZREG * PREG_S2)(a0) + REG_L s3, (SZREG * PREG_S3)(a0) + REG_L s4, (SZREG * PREG_S4)(a0) + REG_L s5, (SZREG * PREG_S5)(a0) + REG_L s6, (SZREG * PREG_S6)(a0) + REG_L s7, (SZREG * PREG_S7)(a0) + REG_L s8, (SZREG * PREG_S8)(a0) + REG_L sp, (SZREG * PREG_SP)(a0) mtc0 v0, COP_0_STATUS_REG # Later the "real" spl value! ITLBNOPFIX jr ra @@ -1505,7 +1476,6 @@ LEAF(fusufault) GET_CPU_PCPU(t0) lw t0, PC_CURTHREAD(t0) lw t0, TD_PCB(t0) - sw zero, U_PCB_ONFAULT(t0) li v0, -1 j ra END(fusufault) @@ -1523,8 +1493,8 @@ LEAF(casuptr) lw t1, PC_CURTHREAD(t1) lw t1, TD_PCB(t1) - lw t2, fusufault - sw t2, U_PCB_ONFAULT(t1) + PTR_LA t2, fusufault + PTR_S t2, U_PCB_ONFAULT(t1) 1: ll v0, 0(a0) /* try to load the old value */ beq v0, a1, 2f /* compare */ @@ -1532,7 +1502,7 @@ LEAF(casuptr) sc t0, 0(a0) /* write if address still locked */ beq t0, zero, 1b /* if it failed, spin */ 2: - sw zero, U_PCB_ONFAULT(t1) /* clean up */ + PTR_S zero, U_PCB_ONFAULT(t1) /* clean up */ j ra END(casuptr) @@ -1560,7 +1530,7 @@ END(octeon_get_shadow) * octeon_set_control(addr, uint32_t val) */ LEAF(octeon_set_control) - .set mips64r2 + .set push or t1, a1, zero /* dmfc0 a1, 9, 7*/ .word 0x40254807 @@ -1570,19 +1540,20 @@ LEAF(octeon_set_control) .word 0x40a54807 jr ra nop - .set mips0 + .set pop END(octeon_set_control) /* * octeon_get_control(addr) */ LEAF(octeon_get_control) + .set push .set mips64r2 /* dmfc0 a1, 9, 7 */ .word 0x40254807 sd a1, 0(a0) jr ra nop - .set mips0 + .set pop END(octeon_get_control) #endif Modified: user/jmallett/octeon/sys/mips/mips/swtch.S ============================================================================== --- user/jmallett/octeon/sys/mips/mips/swtch.S Mon Mar 22 23:27:08 2010 (r205491) +++ user/jmallett/octeon/sys/mips/mips/swtch.S Mon Mar 22 23:31:48 2010 (r205492) @@ -265,7 +265,7 @@ END(savectx) KSEG0TEXT_START; -NON_LEAF(mips_cpu_throw, STAND_FRAME_SIZE, ra) +NON_LEAF(mips_cpu_throw, CALLFRAME_SIZ, ra) mfc0 t0, COP_0_STATUS_REG # t0 = saved status register nop nop @@ -285,7 +285,7 @@ END(mips_cpu_throw) * a2 - mtx * Find the highest priority process and resume it. */ -NON_LEAF(cpu_switch, STAND_FRAME_SIZE, ra) +NON_LEAF(cpu_switch, CALLFRAME_SIZ, ra) mfc0 t0, COP_0_STATUS_REG # t0 = saved status register nop nop @@ -296,9 +296,9 @@ NON_LEAF(cpu_switch, STAND_FRAME_SIZE, r move a3, a0 lw a0, TD_PCB(a0) # load PCB addr of curproc SAVE_U_PCB_CONTEXT(sp, PREG_SP, a0) # save old sp - subu sp, sp, STAND_FRAME_SIZE - sw ra, STAND_RA_OFFSET(sp) - .mask 0x80000000, (STAND_RA_OFFSET - STAND_FRAME_SIZE) + subu sp, sp, CALLFRAME_SIZ + sw ra, CALLFRAME_RA(sp) + .mask 0x80000000, (CALLFRAME_RA - CALLFRAME_SIZ) SAVE_U_PCB_CONTEXT(s0, PREG_S0, a0) # do a 'savectx()' SAVE_U_PCB_CONTEXT(s1, PREG_S1, a0) SAVE_U_PCB_CONTEXT(s2, PREG_S2, a0) Modified: user/jmallett/octeon/sys/mips/mips/trap.c ============================================================================== --- user/jmallett/octeon/sys/mips/mips/trap.c Mon Mar 22 23:27:08 2010 (r205491) +++ user/jmallett/octeon/sys/mips/mips/trap.c Mon Mar 22 23:31:48 2010 (r205492) @@ -102,8 +102,6 @@ __FBSDID("$FreeBSD$"); int trap_debug = 1; #endif -extern unsigned onfault_table[]; - static void log_illegal_instruction(const char *, struct trapframe *); static void log_bad_page_fault(char *, struct trapframe *, int); static void log_frame_dump(struct trapframe *frame); @@ -267,6 +265,7 @@ SYSCTL_INT(_vm, OID_AUTO, allow_unaligne static int emulate_unaligned_access(struct trapframe *frame); extern char *syscallnames[]; +extern void fswintrberr(void); /* XXX */ /* * Handle an exception. @@ -291,6 +290,7 @@ trap(struct trapframe *trapframe) ksiginfo_t ksi; char *msg = NULL; intptr_t addr = 0; + register_t pc; trapdebug_enter(trapframe, 0); @@ -333,9 +333,9 @@ trap(struct trapframe *trapframe) printf("cpuid = %d\n", PCPU_GET(cpuid)); #endif MachTLBGetPID(pid); - printf("badaddr = 0x%0x, pc = 0x%0x, ra = 0x%0x, sp = 0x%0x, sr = 0x%x, pid = %d, ASID = 0x%x\n", - trapframe->badvaddr, trapframe->pc, trapframe->ra, - trapframe->sp, trapframe->sr, + printf("badaddr = %#jx, pc = %#jx, ra = %#jx, sp = %#jx, sr = %jx, pid = %d, ASID = %u\n", + (intmax_t)trapframe->badvaddr, (intmax_t)trapframe->pc, (intmax_t)trapframe->ra, + (intmax_t)trapframe->sp, (intmax_t)trapframe->sr, (curproc ? curproc->p_pid : -1), pid); switch (type & ~T_USER) { @@ -476,22 +476,29 @@ trap(struct trapframe *trapframe) rv = vm_fault(kernel_map, va, ftype, VM_FAULT_NORMAL); if (rv == KERN_SUCCESS) return (trapframe->pc); - if ((i = td->td_pcb->pcb_onfault) != 0) { - td->td_pcb->pcb_onfault = 0; - return (onfault_table[i]); + if (td->td_pcb->pcb_onfault != NULL) { + pc = (register_t)(intptr_t)td->td_pcb->pcb_onfault; + td->td_pcb->pcb_onfault = NULL; + return (pc); } goto err; } - /* + + /* * It is an error for the kernel to access user space except * through the copyin/copyout routines. */ - if ((i = td->td_pcb->pcb_onfault) == 0) *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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