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From: Ruslan Bukin <br@FreeBSD.org>
Date: Mon, 22 Feb 2016 14:19:45 +0000 (UTC)
To: src-committers@freebsd.org, svn-src-all@freebsd.org,
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Subject: svn commit: r295892 - head/sys/riscv/riscv
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Author: br
Date: Mon Feb 22 14:19:45 2016
New Revision: 295892
URL: https://svnweb.freebsd.org/changeset/base/295892

Log:
  Fix comment.

Modified:
  head/sys/riscv/riscv/timer.c

Modified: head/sys/riscv/riscv/timer.c
==============================================================================
--- head/sys/riscv/riscv/timer.c	Mon Feb 22 14:13:05 2016	(r295891)
+++ head/sys/riscv/riscv/timer.c	Mon Feb 22 14:19:45 2016	(r295892)
@@ -145,8 +145,9 @@ riscv_tmr_intr(void *arg)
 
 	/*
 	 * Clear interrupt pending bit.
-	 * Note sip register is unimplemented in Spike simulator,
-	 * so use machine command to clear in mip.
+	 * Note: SIP_STIP bit is not implemented in sip register
+	 * in Spike simulator, so use machine command to clear
+	 * interrupt pending bit in mip.
 	 */
 	machine_command(ECALL_CLEAR_PENDING, 0);