From owner-svn-src-all@FreeBSD.ORG Mon Nov 5 01:05:15 2012 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 047EA3CC; Mon, 5 Nov 2012 01:05:15 +0000 (UTC) (envelope-from sbruno@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) by mx1.freebsd.org (Postfix) with ESMTP id D94048FC0A; Mon, 5 Nov 2012 01:05:14 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.5/8.14.5) with ESMTP id qA515E5j093539; Mon, 5 Nov 2012 01:05:14 GMT (envelope-from sbruno@svn.freebsd.org) Received: (from sbruno@localhost) by svn.freebsd.org (8.14.5/8.14.5/Submit) id qA515E2d093530; Mon, 5 Nov 2012 01:05:14 GMT (envelope-from sbruno@svn.freebsd.org) Message-Id: <201211050105.qA515E2d093530@svn.freebsd.org> From: Sean Bruno Date: Mon, 5 Nov 2012 01:05:14 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-9@freebsd.org Subject: svn commit: r242594 - in stable/9: lib/libpmc sys/dev/hwpmc sys/sys X-SVN-Group: stable-9 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 05 Nov 2012 01:05:15 -0000 Author: sbruno Date: Mon Nov 5 01:05:14 2012 New Revision: 242594 URL: http://svnweb.freebsd.org/changeset/base/242594 Log: MFC r241745,241738,241741 Update hwpmc to support the Xeon class of Sandybridge processors. (Model 0x2D /* Per Intel document 253669-044US 08/2012. */) Update man page crossreferences to sandybridge xeon class Remove trailing whitespace. Added: stable/9/lib/libpmc/pmc.sandybridgexeon.3 - copied, changed from r241738, head/lib/libpmc/pmc.sandybridgexeon.3 Modified: stable/9/lib/libpmc/Makefile stable/9/lib/libpmc/libpmc.c stable/9/lib/libpmc/pmc.ivybridge.3 stable/9/lib/libpmc/pmc.sandybridge.3 stable/9/lib/libpmc/pmc.sandybridgeuc.3 stable/9/sys/dev/hwpmc/hwpmc_core.c stable/9/sys/dev/hwpmc/hwpmc_intel.c stable/9/sys/dev/hwpmc/pmc_events.h stable/9/sys/sys/pmc.h Directory Properties: stable/9/lib/libpmc/ (props changed) stable/9/sys/ (props changed) stable/9/sys/dev/ (props changed) Modified: stable/9/lib/libpmc/Makefile ============================================================================== --- stable/9/lib/libpmc/Makefile Mon Nov 5 00:38:14 2012 (r242593) +++ stable/9/lib/libpmc/Makefile Mon Nov 5 01:05:14 2012 (r242594) @@ -39,6 +39,7 @@ MAN+= pmc.corei7.3 MAN+= pmc.corei7uc.3 MAN+= pmc.sandybridge.3 MAN+= pmc.sandybridgeuc.3 +MAN+= pmc.sandybridgexeon.3 MAN+= pmc.westmere.3 MAN+= pmc.westmereuc.3 MAN+= pmc.tsc.3 Modified: stable/9/lib/libpmc/libpmc.c ============================================================================== --- stable/9/lib/libpmc/libpmc.c Mon Nov 5 00:38:14 2012 (r242593) +++ stable/9/lib/libpmc/libpmc.c Mon Nov 5 01:05:14 2012 (r242594) @@ -192,6 +192,11 @@ static const struct pmc_event_descr sand __PMC_EV_ALIAS_SANDYBRIDGE() }; +static const struct pmc_event_descr sandybridge_xeon_event_table[] = +{ + __PMC_EV_ALIAS_SANDYBRIDGE_XEON() +}; + static const struct pmc_event_descr westmere_event_table[] = { __PMC_EV_ALIAS_WESTMERE() @@ -228,6 +233,7 @@ PMC_MDEP_TABLE(core2, IAP, PMC_CLASS_SOF PMC_MDEP_TABLE(corei7, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); PMC_MDEP_TABLE(ivybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); PMC_MDEP_TABLE(sandybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); +PMC_MDEP_TABLE(sandybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); PMC_MDEP_TABLE(westmere, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); PMC_MDEP_TABLE(k7, K7, PMC_CLASS_SOFT, PMC_CLASS_TSC); PMC_MDEP_TABLE(k8, K8, PMC_CLASS_SOFT, PMC_CLASS_TSC); @@ -265,6 +271,7 @@ PMC_CLASS_TABLE_DESC(core2, IAP, core2, PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap); PMC_CLASS_TABLE_DESC(ivybridge, IAP, ivybridge, iap); PMC_CLASS_TABLE_DESC(sandybridge, IAP, sandybridge, iap); +PMC_CLASS_TABLE_DESC(sandybridge_xeon, IAP, sandybridge_xeon, iap); PMC_CLASS_TABLE_DESC(westmere, IAP, westmere, iap); PMC_CLASS_TABLE_DESC(ucf, UCF, ucf, ucf); PMC_CLASS_TABLE_DESC(corei7uc, UCP, corei7uc, ucp); @@ -569,6 +576,8 @@ static struct pmc_event_alias core2_alia #define ivybridge_aliases_without_iaf core2_aliases_without_iaf #define sandybridge_aliases core2_aliases #define sandybridge_aliases_without_iaf core2_aliases_without_iaf +#define sandybridge_xeon_aliases core2_aliases +#define sandybridge_xeon_aliases_without_iaf core2_aliases_without_iaf #define westmere_aliases core2_aliases #define westmere_aliases_without_iaf core2_aliases_without_iaf @@ -688,7 +697,7 @@ static struct pmc_masks iap_rsp_mask_i7_ NULLMASK }; -static struct pmc_masks iap_rsp_mask_sb_ib[] = { +static struct pmc_masks iap_rsp_mask_sb_sbx_ib[] = { PMCMASK(REQ_DMND_DATA_RD, (1ULL << 0)), PMCMASK(REQ_DMND_RFO, (1ULL << 1)), PMCMASK(REQ_DMND_IFETCH, (1ULL << 2)), @@ -794,9 +803,10 @@ iap_allocate_pmc(enum pmc_event pe, char } else return (-1); } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_SANDYBRIDGE || - cpu_info.pm_cputype == PMC_CPU_INTEL_IVYBRIDGE) { + cpu_info.pm_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON || + cpu_info.pm_cputype == PMC_CPU_INTEL_IVYBRIDGE) { if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { - n = pmc_parse_mask(iap_rsp_mask_sb_ib, p, &rsp); + n = pmc_parse_mask(iap_rsp_mask_sb_sbx_ib, p, &rsp); } else return (-1); } else @@ -2667,6 +2677,10 @@ pmc_event_names_of_class(enum pmc_class ev = sandybridge_event_table; count = PMC_EVENT_TABLE_SIZE(sandybridge); break; + case PMC_CPU_INTEL_SANDYBRIDGE_XEON: + ev = sandybridge_xeon_event_table; + count = PMC_EVENT_TABLE_SIZE(sandybridge_xeon); + break; case PMC_CPU_INTEL_WESTMERE: ev = westmere_event_table; count = PMC_EVENT_TABLE_SIZE(westmere); @@ -2959,6 +2973,9 @@ pmc_init(void) pmc_class_table[n++] = &sandybridgeuc_class_table_descr; PMC_MDEP_INIT_INTEL_V2(sandybridge); break; + case PMC_CPU_INTEL_SANDYBRIDGE_XEON: + PMC_MDEP_INIT_INTEL_V2(sandybridge_xeon); + break; case PMC_CPU_INTEL_WESTMERE: pmc_class_table[n++] = &ucf_class_table_descr; pmc_class_table[n++] = &westmereuc_class_table_descr; @@ -3093,6 +3110,10 @@ _pmc_name_of_event(enum pmc_event pe, en ev = sandybridge_event_table; evfence = sandybridge_event_table + PMC_EVENT_TABLE_SIZE(sandybridge); break; + case PMC_CPU_INTEL_SANDYBRIDGE_XEON: + ev = sandybridge_xeon_event_table; + evfence = sandybridge_xeon_event_table + PMC_EVENT_TABLE_SIZE(sandybridge_xeon); + break; case PMC_CPU_INTEL_WESTMERE: ev = westmere_event_table; evfence = westmere_event_table + PMC_EVENT_TABLE_SIZE(westmere); Modified: stable/9/lib/libpmc/pmc.ivybridge.3 ============================================================================== --- stable/9/lib/libpmc/pmc.ivybridge.3 Mon Nov 5 00:38:14 2012 (r242593) +++ stable/9/lib/libpmc/pmc.ivybridge.3 Mon Nov 5 01:05:14 2012 (r242594) @@ -23,7 +23,7 @@ .\" .\" $FreeBSD$ .\" -.Dd August 24, 2012 +.Dd October 19, 2012 .Dt PMC.IVYBRIDGE 3 .Os .Sh NAME @@ -856,6 +856,7 @@ Dirty L2 cache lines evicted by the MLC .Xr pmc.corei7uc 3 , .Xr pmc.sandybridge 3 , .Xr pmc.sandybridgeuc 3 , +.Xr pmc.sandybridgexeon 3 , .Xr pmc.westmere 3 , .Xr pmc.westmereuc 3 , .Xr pmc.soft 3 , Modified: stable/9/lib/libpmc/pmc.sandybridge.3 ============================================================================== --- stable/9/lib/libpmc/pmc.sandybridge.3 Mon Nov 5 00:38:14 2012 (r242593) +++ stable/9/lib/libpmc/pmc.sandybridge.3 Mon Nov 5 01:05:14 2012 (r242594) @@ -24,7 +24,7 @@ .\" .\" $FreeBSD$ .\" -.Dd February 12, 2012 +.Dd October 19, 2012 .Dt PMC.SANDYBRIDGE 3 .Os .Sh NAME @@ -932,6 +932,7 @@ Split locks in SQ. .Xr pmc.p5 3 , .Xr pmc.p6 3 , .Xr pmc.sandybridgeuc 3 , +.Xr pmc.sandybridgexeon 3 , .Xr pmc.soft 3 , .Xr pmc.tsc 3 , .Xr pmc.ucf 3 , Modified: stable/9/lib/libpmc/pmc.sandybridgeuc.3 ============================================================================== --- stable/9/lib/libpmc/pmc.sandybridgeuc.3 Mon Nov 5 00:38:14 2012 (r242593) +++ stable/9/lib/libpmc/pmc.sandybridgeuc.3 Mon Nov 5 01:05:14 2012 (r242594) @@ -24,7 +24,7 @@ .\" .\" $FreeBSD$ .\" -.Dd February 12, 2012 +.Dd October 19, 2012 .Dt PMC.SANDYBRIDGEUC 3 .Os .Sh NAME @@ -208,6 +208,7 @@ Counts the number of core-outgoing entri .Xr pmc.p5 3 , .Xr pmc.p6 3 , .Xr pmc.sandybridge 3 , +.Xr pmc.sandybridgexeon 3 , .Xr pmc.soft 3 , .Xr pmc.tsc 3 , .Xr pmc.ucf 3 , Copied and modified: stable/9/lib/libpmc/pmc.sandybridgexeon.3 (from r241738, head/lib/libpmc/pmc.sandybridgexeon.3) ============================================================================== --- head/lib/libpmc/pmc.sandybridgexeon.3 Fri Oct 19 17:01:27 2012 (r241738, copy source) +++ stable/9/lib/libpmc/pmc.sandybridgexeon.3 Mon Nov 5 01:05:14 2012 (r242594) @@ -442,147 +442,147 @@ Set Cmask = 1 to count cycles. .It Li PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW .Pq Event 59H , Umask 0FH Cycles with at least one slow LEA uop allocated. -.It Li PARTIAL_RAT_STALLS.MUL_SINGLE_UOP +.It Li PARTIAL_RAT_STALLS.MUL_SINGLE_UOP .Pq Event 59H , Umask 40H Number of Multiply packed/scalar single precision uops allocated. -.It Li RESOURCE_STALLS2.ALL_FL_EMPTY +.It Li RESOURCE_STALLS2.ALL_FL_EMPTY .Pq Event 5BH , Umask 0CH -Cycles stalled due to free list empty. -.It Li RESOURCE_STALLS2.ALL_PRF_CONTROL +Cycles stalled due to free list empty. +.It Li RESOURCE_STALLS2.ALL_PRF_CONTROL .Pq Event 5BH , Umask 0FH Cycles stalled due to control structures full for physical registers. -.It Li RESOURCE_STALLS2.BOB_FULL +.It Li RESOURCE_STALLS2.BOB_FULL .Pq Event 5BH , Umask 40H -Cycles Allocator is stalled due Branch Order Buffer. -.It Li RESOURCE_STALLS2.OOO_RSRC +Cycles Allocator is stalled due Branch Order Buffer. +.It Li RESOURCE_STALLS2.OOO_RSRC .Pq Event 5BH , Umask 4FH -Cycles stalled due to out of order resources full. -.It Li CPL_CYCLES.RING0 +Cycles stalled due to out of order resources full. +.It Li CPL_CYCLES.RING0 .Pq Event 5CH , Umask 01H -Unhalted core cycles when the thread is in ring 0. -.It Li CPL_CYCLES.RING123 +Unhalted core cycles when the thread is in ring 0. +.It Li CPL_CYCLES.RING123 .Pq Event 5CH , Umask 02H Unhalted core cycles when the thread is not in ring 0. .It Li RS_EVENTS.EMPTY_CYCLES .Pq Event 5EH , Umask 01H -Cycles the RS is empty for the thread. -.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD +Cycles the RS is empty for the thread. +.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD .Pq Event 60H , Umask 01H Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles. -.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO +.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO .Pq Event 60H , Umask 04H Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles. -.It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD +.It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD .Pq Event 60H , Umask 08H Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles. -.It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION +.It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION .Pq Event 63H , Umask 01H Cycles in which the L1D and L2 are locked, due to a UC lock or split lock. -.It Li LOCK_CYCLES.CACHE_LOCK_DURATION +.It Li LOCK_CYCLES.CACHE_LOCK_DURATION .Pq Event 63H , Umask 02H -Cycles in which the L1D is locked. -.It Li IDQ.EMPTY +Cycles in which the L1D is locked. +.It Li IDQ.EMPTY .Pq Event 79H , Umask 02H Counts cycles the IDQ is empty. -.It Li IDQ.MITE_UOPS +.It Li IDQ.MITE_UOPS .Pq Event 79H , Umask 04H Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles. -.It Li IDQ.DSB_UOPS +.It Li IDQ.DSB_UOPS .Pq Event 79H , Umask 08H Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles. -.It Li IDQ.MS_DSB_UOPS +.It Li IDQ.MS_DSB_UOPS .Pq Event 79H , Umask 10H Increment each cycle # of uops delivered to IDQ when MS busy by DSB. Set Cmask = 1 to count cycles MS is busy. Set Cmask=1 and Edge =1 to count MS activations. -.It Li IDQ.MS_MITE_UOPS +.It Li IDQ.MS_MITE_UOPS .Pq Event 79H , Umask 20H Increment each cycle # of uops delivered to IDQ when MS is busy by MITE. Set Cmask = 1 to count cycles. -.It Li IDQ.MS_UOPS +.It Li IDQ.MS_UOPS .Pq Event 79H , Umask 30H Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles. -.It Li ICACHE.MISSES +.It Li ICACHE.MISSES .Pq Event 80H , Umask 02H Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses. -.It Li ITLB_MISSES.MISS_CAUSES_A_WALK +.It Li ITLB_MISSES.MISS_CAUSES_A_WALK .Pq Event 85H , Umask 01H -Misses in all ITLB levels that cause page walks. -.It Li ITLB_MISSES.WALK_COMPLETED +Misses in all ITLB levels that cause page walks. +.It Li ITLB_MISSES.WALK_COMPLETED .Pq Event 85H , Umask 02H Misses in all ITLB levels that cause completed page walks. -.It Li ITLB_MISSES.WALK_DURATION +.It Li ITLB_MISSES.WALK_DURATION .Pq Event 85H , Umask 04H -Cycle PMH is busy with a walk. -.It Li ITLB_MISSES.STLB_HIT +Cycle PMH is busy with a walk. +.It Li ITLB_MISSES.STLB_HIT .Pq Event 85H , Umask 10H -Number of cache load STLB hits. No page walk. -.It Li ILD_STALL.LCP +Number of cache load STLB hits. No page walk. +.It Li ILD_STALL.LCP .Pq Event 87H , Umask 01H Stalls caused by changing prefix length of the instruction. -.It Li ILD_STALL.IQ_FULL +.It Li ILD_STALL.IQ_FULL .Pq Event 87H , Umask 04H -Stall cycles due to IQ is full. +Stall cycles due to IQ is full. .It Li BR_INST_EXEC.COND .Pq Event 88H , Umask 01H Qualify conditional near branch instructions executed, but not necessarily retired. -.It Li BR_INST_EXEC.DIRECT_JMP +.It Li BR_INST_EXEC.DIRECT_JMP .Pq Event 88H , Umask 02H Qualify all unconditional near branch instructions excluding calls and indirect branches. -.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET +.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET .Pq Event 88H , Umask 04H Qualify executed indirect near branch instructions that are not calls nor returns. -.It Li BR_INST_EXEC.RETURN_NEAR +.It Li BR_INST_EXEC.RETURN_NEAR .Pq Event 88H , Umask 08H Qualify indirect near branches that have a return mnemonic. -.It Li BR_INST_EXEC.DIRECT_NEAR_CALL +.It Li BR_INST_EXEC.DIRECT_NEAR_CALL .Pq Event 88H , Umask 10H Qualify unconditional near call branch instructions, excluding non call branch, executed. -.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL +.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL .Pq Event 88H , Umask 20H Qualify indirect near calls, including both register and memory indirect, executed. -.It Li BR_INST_EXEC.NONTAKEN +.It Li BR_INST_EXEC.NONTAKEN .Pq Event 88H , Umask 40H -Qualify non-taken near branches executed. -.It Li BR_INST_EXEC.TAKEN +Qualify non-taken near branches executed. +.It Li BR_INST_EXEC.TAKEN .Pq Event 88H , Umask 80H Qualify taken near branches executed. Must combine with 01H,02H, 04H, 08H, 10H, 20H. -.It Li BR_INST_EXE.ALL_BRANCHES +.It Li BR_INST_EXE.ALL_BRANCHES .Pq Event 88H , Umask FFH Counts all near executed branches (not necessarily retired). -.It Li BR_MISP_EXEC.COND +.It Li BR_MISP_EXEC.COND .Pq Event 89H , Umask 01H Qualify conditional near branch instructions mispredicted. -.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET +.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET .Pq Event 89H , Umask 04H Qualify mispredicted indirect near branch instructions that are not calls nor returns. @@ -590,144 +590,144 @@ instructions that are not calls nor retu .Pq Event 89H , Umask 08H Qualify mispredicted indirect near branches that have a return mnemonic. -.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL +.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL .Pq Event 89H , Umask 10H Qualify mispredicted unconditional near call branch instructions, excluding non call branch, executed. -.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL +.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL .Pq Event 89H , Umask 20H Qualify mispredicted indirect near calls, including both register and memory indirect, executed. -.It Li BR_MISP_EXEC.NONTAKEN +.It Li BR_MISP_EXEC.NONTAKEN .Pq Event 89H , Umask 40H Qualify mispredicted non-taken near branches executed,. -.It Li BR_MISP_EXEC.TAKEN +.It Li BR_MISP_EXEC.TAKEN .Pq Event 89H , Umask 80H Qualify mispredicted taken near branches executed. Must combine with 01H,02H, 04H, 08H, 10H, 20H -.It Li BR_MISP_EXEC.ALL_BRANCHES +.It Li BR_MISP_EXEC.ALL_BRANCHES .Pq Event 89H , Umask FFH Counts all near executed branches (not necessarily retired). -.It Li IDQ_UOPS_NOT_DELIVERED.CORE +.It Li IDQ_UOPS_NOT_DELIVERED.CORE .Pq Event 9CH , Umask 01H Count number of non-delivered uops to RAT per thread. -.It Li UOPS_DISPATCHED_PORT.PORT_0 +.It Li UOPS_DISPATCHED_PORT.PORT_0 .Pq Event A1H , Umask 01H -Cycles which a Uop is dispatched on port 0. +Cycles which a Uop is dispatched on port 0. .It Li UOPS_DISPATCHED_PORT.PORT_1 .Pq Event A1H , Umask 02H -Cycles which a Uop is dispatched on port 1. -.It Li UOPS_DISPATCHED_PORT.PORT_2_LD +Cycles which a Uop is dispatched on port 1. +.It Li UOPS_DISPATCHED_PORT.PORT_2_LD .Pq Event A1H , Umask 04H -Cycles which a load uop is dispatched on port 2. -.It Li UOPS_DISPATCHED_PORT.PORT_2_STA +Cycles which a load uop is dispatched on port 2. +.It Li UOPS_DISPATCHED_PORT.PORT_2_STA .Pq Event A1H , Umask 08H Cycles which a store address uop is dispatched on port 2. -.It Li UOPS_DISPATCHED_PORT.PORT_2 +.It Li UOPS_DISPATCHED_PORT.PORT_2 .Pq Event A1H , Umask 0CH -Cycles which a Uop is dispatched on port 2. -.It Li UOPS_DISPATCHED_PORT.PORT_3_LD +Cycles which a Uop is dispatched on port 2. +.It Li UOPS_DISPATCHED_PORT.PORT_3_LD .Pq Event A1H , Umask 10H -Cycles which a load uop is dispatched on port 3. -.It Li UOPS_DISPATCHED_PORT.PORT_3_STA +Cycles which a load uop is dispatched on port 3. +.It Li UOPS_DISPATCHED_PORT.PORT_3_STA .Pq Event A1H , Umask 20H Cycles which a store address uop is dispatched on port 3. -.It Li UOPS_DISPATCHED_PORT.PORT_3 +.It Li UOPS_DISPATCHED_PORT.PORT_3 .Pq Event A1H , Umask 30H -Cycles which a Uop is dispatched on port 3. +Cycles which a Uop is dispatched on port 3. .It Li UOPS_DISPATCHED_PORT.PORT_4 .Pq Event A1H , Umask 40H Cycles which a Uop is dispatched on port 4. -.It Li UOPS_DISPATCHED_PORT.PORT_5 +.It Li UOPS_DISPATCHED_PORT.PORT_5 .Pq Event A1H , Umask 80H -Cycles which a Uop is dispatched on port 5. -.It Li RESOURCE_STALLS.ANY +Cycles which a Uop is dispatched on port 5. +.It Li RESOURCE_STALLS.ANY .Pq Event A2H , Umask 01H Cycles Allocation is stalled due to Resource Related reason. -.It Li RESOURCE_STALLS.LB +.It Li RESOURCE_STALLS.LB .Pq Event A2H , Umask 01H -Counts the cycles of stall due to lack of load buffers. -.It Li RESOURCE_STALLS.RS +Counts the cycles of stall due to lack of load buffers. +.It Li RESOURCE_STALLS.RS .Pq Event A2H , Umask 04H -Cycles stalled due to no eligible RS entry available. -.It Li RESOURCE_STALLS.SB +Cycles stalled due to no eligible RS entry available. +.It Li RESOURCE_STALLS.SB .Pq Event A2H , Umask 08H Cycles stalled due to no store buffers available. (not including draining form sync). -.It Li RESOURCE_STALLS.ROB +.It Li RESOURCE_STALLS.ROB .Pq Event A2H , Umask 10H -Cycles stalled due to re-order buffer full. -.It Li RESOURCE_STALLS.FCSW +Cycles stalled due to re-order buffer full. +.It Li RESOURCE_STALLS.FCSW .Pq Event A2H , Umask 20H -Cycles stalled due to writing the FPU control word. -.It Li RESOURCE_STALLS.MXCSR +Cycles stalled due to writing the FPU control word. +.It Li RESOURCE_STALLS.MXCSR .Pq Event A2H , Umask 40H Cycles stalled due to the MXCSR register rename occurring to close to a previous MXCSR rename. -.It Li RESOURCE_STALLS.OTHER +.It Li RESOURCE_STALLS.OTHER .Pq Event A2H , Umask 80H Cycles stalled while execution was stalled due to other resource issues. -.It Li CYCLE_ACTIVITY.CYCLES_L2_PENDING +.It Li CYCLE_ACTIVITY.CYCLES_L2_PENDING .Pq Event A3H , Umask 01H Cycles with pending L2 miss loads. Set AnyThread to count per core. -.It Li CYCLE_ACTIVITY.CYCLES_L1D_PENDING +.It Li CYCLE_ACTIVITY.CYCLES_L1D_PENDING .Pq Event A3H , Umask 02H Cycles with pending L1 cache miss loads.Set AnyThread to count per core. -.It Li CYCLE_ACTIVITY.CYCLES_NO_DISPATCH +.It Li CYCLE_ACTIVITY.CYCLES_NO_DISPATCH .Pq Event A3H , Umask 04H -Cycles of dispatch stalls. Set AnyThread to count per +Cycles of dispatch stalls. Set AnyThread to count per core. -.It Li DSB2MITE_SWITCHES.COUNT +.It Li DSB2MITE_SWITCHES.COUNT .Pq Event ABH , Umask 01H -Number of DSB to MITE switches. -.It Li DSB2MITE_SWITCHES.PENALTY_CYCLES +Number of DSB to MITE switches. +.It Li DSB2MITE_SWITCHES.PENALTY_CYCLES .Pq Event ABH , Umask 02H -Cycles DSB to MITE switches caused delay. -.It Li DSB_FILL.OTHER_CANCEL +Cycles DSB to MITE switches caused delay. +.It Li DSB_FILL.OTHER_CANCEL .Pq Event ACH , Umask 02H Cases of cancelling valid DSB fill not because of exceeding way limit. -.It Li DSB_FILL.EXCEED_DSB_LINES +.It Li DSB_FILL.EXCEED_DSB_LINES .Pq Event ACH , Umask 08H -DSB Fill encountered > 3 DSB lines. -.It Li DSB_FILL.ALL_CANCEL +DSB Fill encountered > 3 DSB lines. +.It Li DSB_FILL.ALL_CANCEL .Pq Event ACH , Umask 0AH Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit. -.It Li ITLB.ITLB_FLUSH +.It Li ITLB.ITLB_FLUSH .Pq Event AEH , Umask 01H Counts the number of ITLB flushes, includes 4k/2M/4M pages. -.It Li OFFCORE_REQUESTS.DEMAND_DATA_RD +.It Li OFFCORE_REQUESTS.DEMAND_DATA_RD .Pq Event B0H , Umask 01H Demand data read requests sent to uncore. -.It Li OFFCORE_REQUESTS.DEMAND_RFO +.It Li OFFCORE_REQUESTS.DEMAND_RFO .Pq Event B0H , Umask 04H Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM. -.It Li OFFCORE_REQUESTS.ALL_DATA_RD +.It Li OFFCORE_REQUESTS.ALL_DATA_RD .Pq Event B0H , Umask 08H Data read requests sent to uncore (demand and prefetch). -.It Li UOPS_DISPATCHED.THREAD +.It Li UOPS_DISPATCHED.THREAD .Pq Event B1H , Umask 01H Counts total number of uops to be dispatched per- thread each cycle. Set Cmask = 1, INV =1 to count stall cycles. -.It Li UOPS_DISPATCHED.CORE +.It Li UOPS_DISPATCHED.CORE .Pq Event B1H , Umask 02H Counts total number of uops to be dispatched per- core each cycle. -.It Li OFFCORE_REQUESTS_BUFFER.SQ_FULL +.It Li OFFCORE_REQUESTS_BUFFER.SQ_FULL .Pq Event B2H , Umask 01H Offcore requests buffer cannot take more entries for this thread core. @@ -738,47 +738,47 @@ following traits: 1. addressing of the f offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in another page. -.It Li OFF_CORE_RESPONSE_0 +.It Li OFF_CORE_RESPONSE_0 .Pq Event B7H , Umask 01H (Event B7H, Umask 01H) Off-core Response Performance Monitoring; PMC0 only. Requires programming MSR 01A6H -.It Li OFF_CORE_RESPONSE_1 +.It Li OFF_CORE_RESPONSE_1 .Pq Event BBH , Umask 01H (Event BBH, Umask 01H) Off-core Response Performance Monitoring; PMC3 only. Requires programming MSR 01A7H -.It Li TLB_FLUSH.DTLB_THREAD +.It Li TLB_FLUSH.DTLB_THREAD .Pq Event BDH , Umask 01H -DTLB flush attempts of the thread-specific entries. -.It Li TLB_FLUSH.STLB_ANY +DTLB flush attempts of the thread-specific entries. +.It Li TLB_FLUSH.STLB_ANY .Pq Event BDH , Umask 20H -Count number of STLB flush attempts. -.It Li L1D_BLOCKS.BANK_CONFLICT_CYCLES +Count number of STLB flush attempts. +.It Li L1D_BLOCKS.BANK_CONFLICT_CYCLES .Pq Event BFH , Umask 05H Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports. -.It Li INST_RETIRED.ANY_P +.It Li INST_RETIRED.ANY_P .Pq Event C0H , Umask 00H -Number of instructions at retirement. -.It Li INST_RETIRED.ALL +Number of instructions at retirement. +.It Li INST_RETIRED.ALL .Pq Event C0H , Umask 01H Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution. .It Li OTHER_ASSISTS.ITLB_MISS_RETIRED .Pq Event C1H , Umask 02H -Instructions that experienced an ITLB miss. -.It Li OTHER_ASSISTS.AVX_STORE +Instructions that experienced an ITLB miss. +.It Li OTHER_ASSISTS.AVX_STORE .Pq Event C1H , Umask 08H Number of assists associated with 256-bit AVX store operations. -.It Li OTHER_ASSISTS.AVX_TO_SSE +.It Li OTHER_ASSISTS.AVX_TO_SSE .Pq Event C1H , Umask 10H Number of transitions from AVX-256 to legacy SSE when penalty applicable. -.It Li OTHER_ASSISTS.SSE_TO_AVX +.It Li OTHER_ASSISTS.SSE_TO_AVX .Pq Event C1H , Umask 20H Number of transitions from SSE to AVX-256 when penalty applicable. -.It Li UOPS_RETIRED.ALL +.It Li UOPS_RETIRED.ALL .Pq Event C2H , Umask 01H Counts the number of micro-ops retired, Use cmask=1 and invert to count active cycles or stalled @@ -787,7 +787,7 @@ cycles. .Pq Event C2H , Umask 02H Counts the number of retirement slots used each cycle. -.It Li MACHINE_CLEARS.MEMORY_ORDERING +.It Li MACHINE_CLEARS.MEMORY_ORDERING .Pq Event C3H , Umask 02H Counts the number of machine clears due to memory order conflicts. @@ -795,25 +795,25 @@ memory order conflicts. .Pq Event C3H , Umask 04H Counts the number of times that a program writes to a code section. -.It Li MACHINE_CLEARS.MASKMOV +.It Li MACHINE_CLEARS.MASKMOV .Pq Event C3H , Umask 20H Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0. -.It Li BR_INST_RETIRED.ALL_BRANCH +.It Li BR_INST_RETIRED.ALL_BRANCH .Pq Event C4H , Umask 00H -Branch instructions at retirement. -.It Li BR_INST_RETIRED.CONDITIONAL +Branch instructions at retirement. +.It Li BR_INST_RETIRED.CONDITIONAL .Pq Event C4H , Umask 01H Counts the number of conditional branch instructions retired. -.It Li BR_INST_RETIRED.NEAR_CALL +.It Li BR_INST_RETIRED.NEAR_CALL .Pq Event C4H , Umask 02H -Direct and indirect near call instructions retired. -.It Li BR_INST_RETIRED.ALL_BRANCHES +Direct and indirect near call instructions retired. +.It Li BR_INST_RETIRED.ALL_BRANCHES .Pq Event C4H , Umask 04H -Counts the number of branch instructions retired. -.It Li BR_INST_RETIRED.NEAR_RETURN +Counts the number of branch instructions retired. +.It Li BR_INST_RETIRED.NEAR_RETURN .Pq Event C4H , Umask 08H Counts the number of near return instructions retired. @@ -823,16 +823,16 @@ Counts the number of not taken branch in retired. .It Li BR_INST_RETIRED.NEAR_TAKEN .Pq Event C4H , Umask 20H -Number of near taken branches retired. +Number of near taken branches retired. .It Li BR_INST_RETIRED.FAR_BRANCH .Pq Event C4H , Umask 40H -Number of far branches retired. +Number of far branches retired. .It Li BR_MISP_RETIRED.ALL_BRANCHES .Pq Event C5H , Umask 00H -Mispredicted branch instructions at retirement. +Mispredicted branch instructions at retirement. .It Li BR_MISP_RETIRED.CONDITIONAL .Pq Event C5H , Umask 01H -Mispredicted conditional branch instructions retired. +Mispredicted conditional branch instructions retired. .It Li BR_MISP_RETIRED.NEAR_CALL .Pq Event C5H , Umask 02H Direct and indirect mispredicted near call @@ -842,25 +842,25 @@ instructions retired. Mispredicted macro branch instructions retired. .It Li BR_MISP_RETIRED.NOT_TAKEN .Pq Event C5H , Umask 10H -Mispredicted not taken branch instructions retired. +Mispredicted not taken branch instructions retired. .It Li BR_MISP_RETIRED.TAKEN .Pq Event C5H , Umask 20H -Mispredicted taken branch instructions retired. +Mispredicted taken branch instructions retired. .It Li FP_ASSIST.X87_OUTPUT .Pq Event CAH , Umask 02H -Number of X87 assists due to output value. +Number of X87 assists due to output value. .It Li FP_ASSIST.X87_INPUT .Pq Event CAH , Umask 04H -Number of X87 assists due to input value. +Number of X87 assists due to input value. .It Li FP_ASSIST.SIMD_OUTPUT .Pq Event CAH , Umask 08H - Number of SIMD FP assists due to output values. + Number of SIMD FP assists due to output values. .It Li FP_ASSIST.SIMD_INPUT .Pq Event CAH , Umask 10H -Number of SIMD FP assists due to input values. +Number of SIMD FP assists due to input values. .It Li FP_ASSIST.ANY 1EH .Pq Event CAH , Umask -Cycles with any input/output SSE* or FP assists. +Cycles with any input/output SSE* or FP assists. .It Li ROB_MISC_EVENTS.LBR_INSERTS .Pq Event CCH , Umask 20H Count cases of saving new LBR records by @@ -893,27 +893,27 @@ combine with umask 01H, 02H, to produce .Pq Event D0H , Umask Qualify retired memory uops with line split. Must combine with umask 01H, 02H, to produce counts. -.It Li MEM_UOP_RETIRED_ALL +.It Li MEM_UOP_RETIRED_ALL .Pq Event D0H , Umask Qualify any retired memory uops. Must combine with umask 01H, 02H, to produce counts. -.It Li MEM_LOAD_UOPS_RETIRED.L1_HIT +.It Li MEM_LOAD_UOPS_RETIRED.L1_HIT .Pq Event D1H , Umask 01H Retired load uops with L1 cache hits as data sources. -.It Li MEM_LOAD_UOPS_RETIRED.L2_HIT +.It Li MEM_LOAD_UOPS_RETIRED.L2_HIT .Pq Event D1H , Umask 02H Retired load uops with L2 cache hits as data sources. -.It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT +.It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT .Pq Event D1H , Umask 04H -Retired load uops which data sources were data hits +Retired load uops which data sources were data hits in LLC without snoops required. .It Li MEM_LOAD_UOPS_RETIRED.LLC_MISS .Pq Event D1H , Umask 20H Retired load uops which data sources were data missed LLC (excluding unknown data source). -.It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB +.It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB .Pq Event D1H , Umask 40H Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to @@ -930,58 +930,58 @@ correct prediction and this is corrected branch handling mechanisms at the front end. .It Li L2_TRANS.DEMAND_DATA_RD .Pq Event F0H , Umask 01H -Demand Data Read requests that access L2 cache. +Demand Data Read requests that access L2 cache. .It Li L2_TRANS.RFO .Pq Event F0H , Umask 02H -RFO requests that access L2 cache. +RFO requests that access L2 cache. .It Li L2_TRANS.CODE_RD .Pq Event F0H , Umask 04H -L2 cache accesses when fetching instructions. +L2 cache accesses when fetching instructions. .It Li L2_TRANS.ALL_PF .Pq Event F0H , Umask 08H -L2 or LLC HW prefetches that access L2 cache. +L2 or LLC HW prefetches that access L2 cache. .It Li L2_TRANS.L1D_WB .Pq Event F0H , Umask 10H -L1D writebacks that access L2 cache. +L1D writebacks that access L2 cache. .It Li L2_TRANS.L2_FILL .Pq Event F0H , Umask 20H -L2 fill requests that access L2 cache. +L2 fill requests that access L2 cache. .It Li L2_TRANS.L2_WB .Pq Event F0H , Umask 40H -L2 writebacks that access L2 cache. +L2 writebacks that access L2 cache. .It Li L2_TRANS.ALL_REQUESTS .Pq Event F0H , Umask 80H -Transactions accessing L2 pipe. +Transactions accessing L2 pipe. .It Li L2_LINES_IN.I .Pq Event F1H , Umask 01H -L2 cache lines in I state filling L2. +L2 cache lines in I state filling L2. .It Li L2_LINES_IN.S .Pq Event F1H , Umask 02H -L2 cache lines in S state filling L2. -.It Li L2_LINES_IN.E +L2 cache lines in S state filling L2. +.It Li L2_LINES_IN.E .Pq Event F1H , Umask 04H -L2 cache lines in E state filling L2. +L2 cache lines in E state filling L2. .It Li L2_LINES-IN.ALL .Pq Event F1H , Umask 07H -L2 cache lines filling L2. +L2 cache lines filling L2. .It Li L2_LINES_OUT.DEMAND_CLEAN .Pq Event F2H , Umask 01H -Clean L2 cache lines evicted by demand. +Clean L2 cache lines evicted by demand. .It Li L2_LINES_OUT.DEMAND_DIRTY .Pq Event F2H , Umask 02H -Dirty L2 cache lines evicted by demand. +Dirty L2 cache lines evicted by demand. .It Li L2_LINES_OUT.PF_CLEAN .Pq Event F2H , Umask 04H -Clean L2 cache lines evicted by L2 prefetch. +Clean L2 cache lines evicted by L2 prefetch. .It Li L2_LINES_OUT.PF_DIRTY .Pq Event F2H , Umask 08H -Dirty L2 cache lines evicted by L2 prefetch. +Dirty L2 cache lines evicted by L2 prefetch. .It Li L2_LINES_OUT.DIRTY_ALL .Pq Event F2H , Umask 0AH -Dirty L2 cache lines filling the L2. +Dirty L2 cache lines filling the L2. .It Li SQ_MISC.SPLIT_LOCK .Pq Event F4H , Umask 10H -Split locks in SQ. +Split locks in SQ. .El .Sh SEE ALSO .Xr pmc 3 , Modified: stable/9/sys/dev/hwpmc/hwpmc_core.c ============================================================================== --- stable/9/sys/dev/hwpmc/hwpmc_core.c Mon Nov 5 00:38:14 2012 (r242593) +++ stable/9/sys/dev/hwpmc/hwpmc_core.c Mon Nov 5 01:05:14 2012 (r242594) @@ -558,7 +558,8 @@ struct iap_event_descr { #define IAP_F_WM (1 << 5) /* CPU: Westmere */ #define IAP_F_SB (1 << 6) /* CPU: Sandy Bridge */ #define IAP_F_IB (1 << 7) /* CPU: Ivy Bridge */ -#define IAP_F_FM (1 << 8) /* Fixed mask */ +#define IAP_F_SBX (1 << 8) /* CPU: Sandy Bridge Xeon */ +#define IAP_F_FM (1 << 9) /* Fixed mask */ #define IAP_F_ALLCPUSCORE2 \ (IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA) @@ -598,12 +599,15 @@ static struct iap_event_descr iap_events IAPDESCR(02H_81H, 0x02, 0x81, IAP_F_FM | IAP_F_CA), IAPDESCR(03H_00H, 0x03, 0x00, IAP_F_FM | IAP_F_CC), - IAPDESCR(03H_01H, 0x03, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB), + IAPDESCR(03H_01H, 0x03, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | + IAP_F_SBX), IAPDESCR(03H_02H, 0x03, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_WM | IAP_F_SB | IAP_F_IB), + IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(03H_04H, 0x03, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), - IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB), - IAPDESCR(03H_10H, 0x03, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB), + IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | + IAP_F_SBX), + IAPDESCR(03H_10H, 0x03, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | + IAP_F_SBX), IAPDESCR(03H_20H, 0x03, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(04H_00H, 0x04, 0x00, IAP_F_FM | IAP_F_CC), @@ -613,8 +617,10 @@ static struct iap_event_descr iap_events IAPDESCR(04H_08H, 0x04, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(05H_00H, 0x05, 0x00, IAP_F_FM | IAP_F_CC), - IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB), - IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_WM | IAP_F_SB | IAP_F_IB), + IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_WM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), IAPDESCR(05H_03H, 0x05, 0x03, IAP_F_FM | IAP_F_I7O), IAPDESCR(06H_00H, 0x06, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2 | @@ -627,24 +633,26 @@ static struct iap_event_descr iap_events IAPDESCR(07H_00H, 0x07, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), IAPDESCR(07H_01H, 0x07, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | - IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), + IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(07H_02H, 0x07, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(07H_03H, 0x07, 0x03, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(07H_06H, 0x07, 0x06, IAP_F_FM | IAP_F_CA), - IAPDESCR(07H_08H, 0x07, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_SB), + IAPDESCR(07H_08H, 0x07, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_SB | + IAP_F_SBX), IAPDESCR(08H_01H, 0x08, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_I7 | IAP_F_WM | IAP_F_SB), + IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX), IAPDESCR(08H_02H, 0x08, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_I7 | IAP_F_WM | IAP_F_SB), + IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX), IAPDESCR(08H_04H, 0x08, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_WM | IAP_F_SB), + IAP_F_WM | IAP_F_SB | IAP_F_SBX), IAPDESCR(08H_05H, 0x08, 0x05, IAP_F_FM | IAP_F_CA), IAPDESCR(08H_06H, 0x08, 0x06, IAP_F_FM | IAP_F_CA), IAPDESCR(08H_07H, 0x08, 0x07, IAP_F_FM | IAP_F_CA), IAPDESCR(08H_08H, 0x08, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(08H_09H, 0x08, 0x09, IAP_F_FM | IAP_F_CA), - IAPDESCR(08H_10H, 0x08, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), + IAPDESCR(08H_10H, 0x08, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | + IAP_F_SBX), IAPDESCR(08H_20H, 0x08, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(08H_40H, 0x08, 0x40, IAP_F_FM | IAP_F_I7O), IAPDESCR(08H_80H, 0x08, 0x80, IAP_F_FM | IAP_F_I7), @@ -666,10 +674,11 @@ static struct iap_event_descr iap_events IAPDESCR(0CH_02H, 0x0C, 0x02, IAP_F_FM | IAP_F_CC2), IAPDESCR(0CH_03H, 0x0C, 0x03, IAP_F_FM | IAP_F_CA), - IAPDESCR(0DH_03H, 0x0D, 0x03, IAP_F_FM | IAP_F_SB), - IAPDESCR(0DH_40H, 0x0D, 0x40, IAP_F_FM | IAP_F_SB), + IAPDESCR(0DH_03H, 0x0D, 0x03, IAP_F_FM | IAP_F_SB | IAP_F_SBX), + IAPDESCR(0DH_40H, 0x0D, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), - IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), + IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), IAPDESCR(0EH_02H, 0x0E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(0EH_10H, 0x0E, 0x10, IAP_F_FM | IAP_F_IB), IAPDESCR(0EH_20H, 0x0E, 0x20, IAP_F_FM | IAP_F_IB), @@ -684,19 +693,24 @@ static struct iap_event_descr iap_events IAPDESCR(10H_00H, 0x10, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(10H_01H, 0x10, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | - IAP_F_WM | IAP_F_SB), + IAP_F_WM | IAP_F_SB | IAP_F_SBX), IAPDESCR(10H_02H, 0x10, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(10H_04H, 0x10, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(10H_08H, 0x10, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), - IAPDESCR(10H_10H, 0x10, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), - IAPDESCR(10H_20H, 0x10, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), - IAPDESCR(10H_40H, 0x10, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), - IAPDESCR(10H_80H, 0x10, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), + IAPDESCR(10H_10H, 0x10, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | + IAP_F_SBX), + IAPDESCR(10H_20H, 0x10, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | + IAP_F_SBX), + IAPDESCR(10H_40H, 0x10, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | + IAP_F_SBX), + IAPDESCR(10H_80H, 0x10, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | + IAP_F_SBX), IAPDESCR(10H_81H, 0x10, 0x81, IAP_F_FM | IAP_F_CA), IAPDESCR(11H_00H, 0x11, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), - IAPDESCR(11H_01H, 0x11, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_SB), - IAPDESCR(11H_02H, 0x11, 0x02, IAP_F_FM | IAP_F_SB), + IAPDESCR(11H_01H, 0x11, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_SB | + IAP_F_SBX), + IAPDESCR(11H_02H, 0x11, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX), IAPDESCR(11H_81H, 0x11, 0x81, IAP_F_FM | IAP_F_CA), IAPDESCR(12H_00H, 0x12, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), @@ -718,10 +732,11 @@ static struct iap_event_descr iap_events IAPDESCR(14H_00H, 0x14, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), IAPDESCR(14H_01H, 0x14, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | - IAP_F_WM | IAP_F_SB | IAP_F_IB), + IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(14H_02H, 0x14, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), - IAPDESCR(17H_01H, 0x17, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), + IAPDESCR(17H_01H, 0x17, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | + IAP_F_SBX), IAPDESCR(18H_00H, 0x18, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(18H_01H, 0x18, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), @@ -743,18 +758,29 @@ static struct iap_event_descr iap_events IAPDESCR(23H, 0x23, IAP_M_CORE, IAP_F_ALLCPUSCORE2), IAPDESCR(24H, 0x24, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), - IAPDESCR(24H_01H, 0x24, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), + IAPDESCR(24H_01H, 0x24, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), IAPDESCR(24H_02H, 0x24, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), - IAPDESCR(24H_03H, 0x24, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), - IAPDESCR(24H_04H, 0x24, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), - IAPDESCR(24H_08H, 0x24, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), - IAPDESCR(24H_0CH, 0x24, 0x0C, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), - IAPDESCR(24H_10H, 0x24, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), - IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), - IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), - IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), - IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), - IAPDESCR(24H_C0H, 0x24, 0xC0, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), + IAPDESCR(24H_03H, 0x24, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(24H_04H, 0x24, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(24H_08H, 0x24, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(24H_0CH, 0x24, 0x0C, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(24H_10H, 0x24, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***