From owner-svn-src-stable-12@freebsd.org Wed Dec 16 08:03:08 2020 Return-Path: Delivered-To: svn-src-stable-12@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id 6DA714B4177; Wed, 16 Dec 2020 08:03:08 +0000 (UTC) (envelope-from wulf@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4CwngJ2djWz4Y6l; Wed, 16 Dec 2020 08:03:08 +0000 (UTC) (envelope-from wulf@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4D3A022D12; Wed, 16 Dec 2020 08:03:08 +0000 (UTC) (envelope-from wulf@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id 0BG83898034709; Wed, 16 Dec 2020 08:03:08 GMT (envelope-from wulf@FreeBSD.org) Received: (from wulf@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id 0BG837MR034707; Wed, 16 Dec 2020 08:03:07 GMT (envelope-from wulf@FreeBSD.org) Message-Id: <202012160803.0BG837MR034707@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: wulf set sender to wulf@FreeBSD.org using -f From: Vladimir Kondratyev Date: Wed, 16 Dec 2020 08:03:07 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-12@freebsd.org Subject: svn commit: r368690 - stable/12/sys/dev/ichiic X-SVN-Group: stable-12 X-SVN-Commit-Author: wulf X-SVN-Commit-Paths: stable/12/sys/dev/ichiic X-SVN-Commit-Revision: 368690 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-stable-12@freebsd.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: SVN commit messages for only the 12-stable src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 16 Dec 2020 08:03:08 -0000 Author: wulf Date: Wed Dec 16 08:03:07 2020 New Revision: 368690 URL: https://svnweb.freebsd.org/changeset/base/368690 Log: MFC r368366 ig4(4): Add PCI IDs for Intel Tiger Lake Submitted by: Neel Chauhan Differential Revision: https://reviews.freebsd.org/D27483 Modified: stable/12/sys/dev/ichiic/ig4_iic.c stable/12/sys/dev/ichiic/ig4_pci.c stable/12/sys/dev/ichiic/ig4_var.h Directory Properties: stable/12/ (props changed) Modified: stable/12/sys/dev/ichiic/ig4_iic.c ============================================================================== --- stable/12/sys/dev/ichiic/ig4_iic.c Wed Dec 16 07:59:47 2020 (r368689) +++ stable/12/sys/dev/ichiic/ig4_iic.c Wed Dec 16 08:03:07 2020 (r368690) @@ -119,6 +119,12 @@ static const struct ig4_hw ig4iic_hw[] = { .ic_clock_rate = 216, .sda_hold_time = 230, }, + [IG4_TIGERLAKE] = { + .ic_clock_rate = 133, + .sda_fall_time = 171, + .scl_fall_time = 208, + .sda_hold_time = 42, + }, }; static int ig4iic_set_config(ig4iic_softc_t *sc, bool reset); Modified: stable/12/sys/dev/ichiic/ig4_pci.c ============================================================================== --- stable/12/sys/dev/ichiic/ig4_pci.c Wed Dec 16 07:59:47 2020 (r368689) +++ stable/12/sys/dev/ichiic/ig4_pci.c Wed Dec 16 08:03:07 2020 (r368690) @@ -121,6 +121,21 @@ static int ig4iic_pci_detach(device_t dev); #define PCI_CHIP_COMETLAKE_V_I2C_1 0xa3e18086 #define PCI_CHIP_COMETLAKE_V_I2C_2 0xa3e28086 #define PCI_CHIP_COMETLAKE_V_I2C_3 0xa3e38086 +#define PCI_CHIP_TIGERLAKE_H_I2C_0 0x43d88086 +#define PCI_CHIP_TIGERLAKE_H_I2C_1 0x43e88086 +#define PCI_CHIP_TIGERLAKE_H_I2C_2 0x43e98086 +#define PCI_CHIP_TIGERLAKE_H_I2C_3 0x43ea8086 +#define PCI_CHIP_TIGERLAKE_H_I2C_4 0x43eb8086 +#define PCI_CHIP_TIGERLAKE_H_I2C_5 0x43ad8086 +#define PCI_CHIP_TIGERLAKE_H_I2C_6 0x43ae8086 +#define PCI_CHIP_TIGERLAKE_LP_I2C_0 0xa0c58086 +#define PCI_CHIP_TIGERLAKE_LP_I2C_1 0xa0c68086 +#define PCI_CHIP_TIGERLAKE_LP_I2C_2 0xa0d88086 +#define PCI_CHIP_TIGERLAKE_LP_I2C_3 0xa0d98086 +#define PCI_CHIP_TIGERLAKE_LP_I2C_4 0xa0e88086 +#define PCI_CHIP_TIGERLAKE_LP_I2C_5 0xa0e98086 +#define PCI_CHIP_TIGERLAKE_LP_I2C_6 0xa0ea8086 +#define PCI_CHIP_TIGERLAKE_LP_I2C_7 0xa0eb8086 struct ig4iic_pci_device { uint32_t devid; @@ -184,6 +199,21 @@ static struct ig4iic_pci_device ig4iic_pci_devices[] = { PCI_CHIP_COMETLAKE_V_I2C_1, "Intel Comet Lake-V I2C Controller-1", IG4_CANNONLAKE}, { PCI_CHIP_COMETLAKE_V_I2C_2, "Intel Comet Lake-V I2C Controller-2", IG4_CANNONLAKE}, { PCI_CHIP_COMETLAKE_V_I2C_3, "Intel Comet Lake-V I2C Controller-3", IG4_CANNONLAKE}, + { PCI_CHIP_TIGERLAKE_H_I2C_0, "Intel Tiger Lake-H I2C Controller-0", IG4_TIGERLAKE}, + { PCI_CHIP_TIGERLAKE_H_I2C_1, "Intel Tiger Lake-H I2C Controller-1", IG4_TIGERLAKE}, + { PCI_CHIP_TIGERLAKE_H_I2C_2, "Intel Tiger Lake-H I2C Controller-2", IG4_TIGERLAKE}, + { PCI_CHIP_TIGERLAKE_H_I2C_3, "Intel Tiger Lake-H I2C Controller-3", IG4_TIGERLAKE}, + { PCI_CHIP_TIGERLAKE_H_I2C_4, "Intel Tiger Lake-H I2C Controller-4", IG4_TIGERLAKE}, + { PCI_CHIP_TIGERLAKE_H_I2C_5, "Intel Tiger Lake-H I2C Controller-5", IG4_TIGERLAKE}, + { PCI_CHIP_TIGERLAKE_H_I2C_6, "Intel Tiger Lake-H I2C Controller-6", IG4_TIGERLAKE}, + { PCI_CHIP_TIGERLAKE_LP_I2C_0, "Intel Tiger Lake-LP I2C Controller-0", IG4_SKYLAKE}, + { PCI_CHIP_TIGERLAKE_LP_I2C_1, "Intel Tiger Lake-LP I2C Controller-1", IG4_SKYLAKE}, + { PCI_CHIP_TIGERLAKE_LP_I2C_2, "Intel Tiger Lake-LP I2C Controller-2", IG4_SKYLAKE}, + { PCI_CHIP_TIGERLAKE_LP_I2C_3, "Intel Tiger Lake-LP I2C Controller-3", IG4_SKYLAKE}, + { PCI_CHIP_TIGERLAKE_LP_I2C_4, "Intel Tiger Lake-LP I2C Controller-4", IG4_SKYLAKE}, + { PCI_CHIP_TIGERLAKE_LP_I2C_5, "Intel Tiger Lake-LP I2C Controller-5", IG4_SKYLAKE}, + { PCI_CHIP_TIGERLAKE_LP_I2C_6, "Intel Tiger Lake-LP I2C Controller-6", IG4_SKYLAKE}, + { PCI_CHIP_TIGERLAKE_LP_I2C_7, "Intel Tiger Lake-LP I2C Controller-7", IG4_SKYLAKE}, }; static int Modified: stable/12/sys/dev/ichiic/ig4_var.h ============================================================================== --- stable/12/sys/dev/ichiic/ig4_var.h Wed Dec 16 07:59:47 2020 (r368689) +++ stable/12/sys/dev/ichiic/ig4_var.h Wed Dec 16 08:03:07 2020 (r368690) @@ -43,10 +43,17 @@ #include "pci_if.h" #include "iicbus_if.h" -enum ig4_vers { IG4_HASWELL, IG4_ATOM, IG4_SKYLAKE, IG4_APL, IG4_CANNONLAKE }; +enum ig4_vers { + IG4_HASWELL, + IG4_ATOM, + IG4_SKYLAKE, + IG4_APL, + IG4_CANNONLAKE, + IG4_TIGERLAKE +}; + /* Controller has additional registers */ -#define IG4_HAS_ADDREGS(vers) ((vers) == IG4_SKYLAKE || \ - (vers) == IG4_APL || (vers) == IG4_CANNONLAKE) +#define IG4_HAS_ADDREGS(vers) ((vers) >= IG4_SKYLAKE) struct ig4_hw { uint32_t ic_clock_rate; /* MHz */