From owner-p4-projects@FreeBSD.ORG Tue Jun 1 15:08:12 2004 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id 256BF16A4D0; Tue, 1 Jun 2004 15:08:12 -0700 (PDT) Delivered-To: perforce@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id EC35C16A4CE for ; Tue, 1 Jun 2004 15:08:11 -0700 (PDT) Received: from repoman.freebsd.org (repoman.freebsd.org [216.136.204.115]) by mx1.FreeBSD.org (Postfix) with ESMTP id EA27443D1D for ; Tue, 1 Jun 2004 15:08:11 -0700 (PDT) (envelope-from peter@freebsd.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.12.11/8.12.11) with ESMTP id i51M8Arc012513 for ; Tue, 1 Jun 2004 15:08:10 -0700 (PDT) (envelope-from peter@freebsd.org) Received: (from perforce@localhost) by repoman.freebsd.org (8.12.11/8.12.11/Submit) id i51M8A0v012510 for perforce@freebsd.org; Tue, 1 Jun 2004 15:08:10 -0700 (PDT) (envelope-from peter@freebsd.org) Date: Tue, 1 Jun 2004 15:08:10 -0700 (PDT) Message-Id: <200406012208.i51M8A0v012510@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to peter@freebsd.org using -f From: Peter Wemm To: Perforce Change Reviews Subject: PERFORCE change 53981 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 01 Jun 2004 22:08:12 -0000 http://perforce.freebsd.org/chv.cgi?CH=53981 Change 53981 by peter@peter_daintree on 2004/06/01 15:07:53 IFC @53975 Affected files ... .. //depot/projects/hammer/sys/amd64/acpica/madt.c#33 integrate .. //depot/projects/hammer/sys/amd64/amd64/apic_vector.S#22 integrate .. //depot/projects/hammer/sys/amd64/amd64/exception.S#30 integrate .. //depot/projects/hammer/sys/amd64/amd64/genassym.c#35 integrate .. //depot/projects/hammer/sys/amd64/amd64/identcpu.c#29 integrate .. //depot/projects/hammer/sys/amd64/amd64/intr_machdep.c#20 integrate .. //depot/projects/hammer/sys/amd64/amd64/io_apic.c#26 integrate .. //depot/projects/hammer/sys/amd64/amd64/legacy.c#11 integrate .. //depot/projects/hammer/sys/amd64/amd64/mem.c#19 integrate .. //depot/projects/hammer/sys/amd64/amd64/mptable.c#26 integrate .. //depot/projects/hammer/sys/amd64/amd64/nexus.c#23 integrate .. //depot/projects/hammer/sys/amd64/amd64/pmap.c#70 integrate .. //depot/projects/hammer/sys/amd64/amd64/support.S#24 integrate .. //depot/projects/hammer/sys/amd64/amd64/vm_machdep.c#43 integrate .. //depot/projects/hammer/sys/amd64/conf/GENERIC#42 integrate .. //depot/projects/hammer/sys/amd64/include/_stdint.h#6 integrate .. //depot/projects/hammer/sys/amd64/include/cputypes.h#7 integrate .. //depot/projects/hammer/sys/amd64/include/profile.h#18 integrate .. //depot/projects/hammer/sys/amd64/isa/atpic.c#41 integrate .. //depot/projects/hammer/sys/amd64/isa/atpic_vector.S#20 integrate .. //depot/projects/hammer/sys/amd64/isa/clock.c#24 integrate .. //depot/projects/hammer/sys/amd64/pci/pci_bus.c#20 integrate Differences ... ==== //depot/projects/hammer/sys/amd64/acpica/madt.c#33 (text+ko) ==== @@ -67,8 +67,8 @@ struct lapic_info { u_int la_present:1; u_int la_enabled:1; - u_int la_apic_id:8; -} lapics[NLAPICS + 1]; + u_int la_acpi_id:8; +} lapics[NLAPICS]; static int madt_found_sci_override; static MULTIPLE_APIC_TABLE *madt; @@ -447,14 +447,14 @@ printf("MADT: Found CPU APIC ID %d ACPI ID %d: %s\n", proc->LocalApicId, proc->ProcessorId, proc->ProcessorEnabled ? "enabled" : "disabled"); - if (proc->ProcessorId > NLAPICS) + if (proc->LocalApicId >= NLAPICS) panic("%s: CPU ID %d too high", __func__, - proc->ProcessorId); - la = &lapics[proc->ProcessorId]; + proc->LocalApicId); + la = &lapics[proc->LocalApicId]; KASSERT(la->la_present == 0, - ("Duplicate local ACPI ID %d", proc->ProcessorId)); + ("Duplicate local APIC ID %d", proc->LocalApicId)); la->la_present = 1; - la->la_apic_id = proc->LocalApicId; + la->la_acpi_id = proc->ProcessorId; if (proc->ProcessorEnabled) { la->la_enabled = 1; lapic_create(proc->LocalApicId, 0); @@ -545,14 +545,20 @@ static int madt_find_cpu(u_int acpi_id, u_int *apic_id) { + int i; - if (!lapics[acpi_id].la_present) - return (ENOENT); - *apic_id = lapics[acpi_id].la_apic_id; - if (lapics[acpi_id].la_enabled) - return (0); - else - return (ENXIO); + for (i = 0; i < NLAPICS; i++) { + if (!lapics[i].la_present) + continue; + if (lapics[i].la_acpi_id != acpi_id) + continue; + *apic_id = i; + if (lapics[i].la_enabled) + return (0); + else + return (ENXIO); + } + return (ENOENT); } /* @@ -752,8 +758,9 @@ static void madt_set_ids(void *dummy) { + struct lapic_info *la; struct pcpu *pc; - u_int i, j; + u_int i; if (madt == NULL) return; @@ -762,19 +769,14 @@ continue; pc = pcpu_find(i); KASSERT(pc != NULL, ("no pcpu data for CPU %d", i)); - for (j = 0; j < NLAPICS + 1; j++) { - if (!lapics[j].la_present || !lapics[j].la_enabled) - continue; - if (lapics[j].la_apic_id == pc->pc_apic_id) { - pc->pc_acpi_id = j; - if (bootverbose) - printf("APIC: CPU %u has ACPI ID %u\n", - i, j); - break; - } - } - if (j == NLAPICS + 1) - panic("Unable to find ACPI ID for CPU %d", i); + la = &lapics[pc->pc_apic_id]; + if (!la->la_present || !la->la_enabled) + panic("APIC: CPU with APIC ID %u is not enabled", + pc->pc_apic_id); + pc->pc_acpi_id = la->la_acpi_id; + if (bootverbose) + printf("APIC: CPU %u has ACPI ID %u\n", i, + la->la_acpi_id); } } SYSINIT(madt_set_ids, SI_SUB_CPU, SI_ORDER_ANY, madt_set_ids, NULL) ==== //depot/projects/hammer/sys/amd64/amd64/apic_vector.S#22 (text+ko) ==== ==== //depot/projects/hammer/sys/amd64/amd64/exception.S#30 (text+ko) ==== ==== //depot/projects/hammer/sys/amd64/amd64/genassym.c#35 (text+ko) ==== ==== //depot/projects/hammer/sys/amd64/amd64/identcpu.c#29 (text+ko) ==== @@ -90,7 +90,10 @@ static char cpu_brand[48]; -static struct cpu_nameclass amd64_cpus[] = { +static struct { + char *cpu_name; + int cpu_class; +} amd64_cpus[] = { { "Clawhammer", CPUCLASS_K8 }, /* CPU_CLAWHAMMER */ { "Sledgehammer", CPUCLASS_K8 }, /* CPU_SLEDGEHAMMER */ }; ==== //depot/projects/hammer/sys/amd64/amd64/intr_machdep.c#20 (text+ko) ==== ==== //depot/projects/hammer/sys/amd64/amd64/io_apic.c#26 (text+ko) ==== @@ -126,6 +126,7 @@ static void ioapic_suspend(struct intsrc *isrc); static void ioapic_resume(struct intsrc *isrc); static void ioapic_program_destination(struct ioapic_intsrc *intpin); +static void ioapic_program_intpin(struct ioapic_intsrc *intpin); static void ioapic_setup_mixed_mode(struct ioapic_intsrc *intpin); static STAILQ_HEAD(,ioapic) ioapic_list = STAILQ_HEAD_INITIALIZER(ioapic_list); @@ -135,7 +136,7 @@ ioapic_suspend, ioapic_resume, ioapic_config_intr }; -static int current_cluster, logical_clusters, next_ioapic_base; +static int bsp_id, current_cluster, logical_clusters, next_ioapic_base; static u_int mixed_mode_enabled, next_id, program_logical_dest; #if defined(NO_MIXED_MODE) || !defined(DEV_ATPIC) static int mixed_mode_active = 0; @@ -208,13 +209,88 @@ } /* + * Completely program an intpin based on the data in its interrupt source + * structure. + */ +static void +ioapic_program_intpin(struct ioapic_intsrc *intpin) +{ + struct ioapic *io = (struct ioapic *)intpin->io_intsrc.is_pic; + uint32_t low, high, value; + + /* + * For pins routed via mixed mode or disabled, just ensure that + * they are masked. + */ + if (intpin->io_dest == DEST_EXTINT || + intpin->io_vector == VECTOR_DISABLED) { + low = ioapic_read(io->io_addr, + IOAPIC_REDTBL_LO(intpin->io_intpin)); + if ((low & IOART_INTMASK) == IOART_INTMCLR) + ioapic_write(io->io_addr, + IOAPIC_REDTBL_LO(intpin->io_intpin), + low | IOART_INTMSET); + return; + } + + /* Set the destination. */ + if (intpin->io_dest == DEST_NONE) { + low = IOART_DESTPHY; + high = bsp_id << APIC_ID_SHIFT; + } else { + low = IOART_DESTLOG; + high = (intpin->io_dest << APIC_ID_CLUSTER_SHIFT | + APIC_ID_CLUSTER_ID) << APIC_ID_SHIFT; + } + + /* Program the rest of the low word. */ + if (intpin->io_edgetrigger) + low |= IOART_TRGREDG; + else + low |= IOART_TRGRLVL; + if (intpin->io_activehi) + low |= IOART_INTAHI; + else + low |= IOART_INTALO; + if (intpin->io_masked) + low |= IOART_INTMSET; + switch (intpin->io_vector) { + case VECTOR_EXTINT: + KASSERT(intpin->io_edgetrigger, + ("EXTINT not edge triggered")); + low |= IOART_DELEXINT; + break; + case VECTOR_NMI: + KASSERT(intpin->io_edgetrigger, + ("NMI not edge triggered")); + low |= IOART_DELNMI; + break; + case VECTOR_SMI: + KASSERT(intpin->io_edgetrigger, + ("SMI not edge triggered")); + low |= IOART_DELSMI; + break; + default: + low |= IOART_DELLOPRI | apic_irq_to_idt(intpin->io_vector); + } + + /* Write the values to the APIC. */ + mtx_lock_spin(&icu_lock); + ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), low); + value = ioapic_read(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin)); + value &= ~IOART_DEST; + value |= high; + ioapic_write(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin), value); + mtx_unlock_spin(&icu_lock); +} + +/* * Program an individual intpin's logical destination. */ static void ioapic_program_destination(struct ioapic_intsrc *intpin) { struct ioapic *io = (struct ioapic *)intpin->io_intsrc.is_pic; - uint32_t value; KASSERT(intpin->io_dest != DEST_NONE, ("intpin not assigned to a cluster")); @@ -229,17 +305,7 @@ printf("IRQ %u", intpin->io_vector); printf(") to cluster %u\n", intpin->io_dest); } - mtx_lock_spin(&icu_lock); - value = ioapic_read(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin)); - value &= ~IOART_DESTMOD; - value |= IOART_DESTLOG; - ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), value); - value = ioapic_read(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin)); - value &= ~IOART_DEST; - value |= (intpin->io_dest << APIC_ID_CLUSTER_SHIFT | - APIC_ID_CLUSTER_ID) << APIC_ID_SHIFT; - ioapic_write(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin), value); - mtx_unlock_spin(&icu_lock); + ioapic_program_intpin(intpin); } static void @@ -339,7 +405,7 @@ ioapic_resume(struct intsrc *isrc) { - TODO; + ioapic_program_intpin((struct ioapic_intsrc *)isrc); } /* @@ -631,6 +697,7 @@ printf("ioapic%u irqs %u-%u on motherboard\n", io->io_id, flags >> 4, flags & 0xf, io->io_intbase, io->io_intbase + io->io_numintr - 1); + bsp_id = PCPU_GET(apic_id); for (i = 0, pin = io->io_pins; i < io->io_numintr; i++, pin++) { /* * Finish initializing the pins by programming the vectors @@ -638,63 +705,18 @@ */ if (pin->io_vector == VECTOR_DISABLED) continue; - flags = IOART_DESTPHY; - if (pin->io_edgetrigger) - flags |= IOART_TRGREDG; - else - flags |= IOART_TRGRLVL; - if (pin->io_activehi) - flags |= IOART_INTAHI; - else - flags |= IOART_INTALO; - if (pin->io_masked) - flags |= IOART_INTMSET; - switch (pin->io_vector) { - case VECTOR_EXTINT: - KASSERT(pin->io_edgetrigger, - ("EXTINT not edge triggered")); - flags |= IOART_DELEXINT; - break; - case VECTOR_NMI: - KASSERT(pin->io_edgetrigger, - ("NMI not edge triggered")); - flags |= IOART_DELNMI; - break; - case VECTOR_SMI: - KASSERT(pin->io_edgetrigger, - ("SMI not edge triggered")); - flags |= IOART_DELSMI; - break; - default: - flags |= IOART_DELLOPRI | - apic_irq_to_idt(pin->io_vector); - } - mtx_lock_spin(&icu_lock); - ioapic_write(apic, IOAPIC_REDTBL_LO(i), flags); - + ioapic_program_intpin(pin); + if (pin->io_vector >= NUM_IO_INTS) + continue; /* - * Route interrupts to the BSP by default using physical - * addressing. Vectored interrupts get readdressed using - * logical IDs to CPU clusters when they are enabled. + * Route IRQ0 via the 8259A using mixed mode if mixed mode + * is available and turned on. */ - flags = ioapic_read(apic, IOAPIC_REDTBL_HI(i)); - flags &= ~IOART_DEST; - flags |= PCPU_GET(apic_id) << APIC_ID_SHIFT; - ioapic_write(apic, IOAPIC_REDTBL_HI(i), flags); - mtx_unlock_spin(&icu_lock); - if (pin->io_vector < NUM_IO_INTS) { - - /* - * Route IRQ0 via the 8259A using mixed mode if - * mixed mode is available and turned on. - */ - if (pin->io_vector == 0 && mixed_mode_active && - mixed_mode_enabled) - ioapic_setup_mixed_mode(pin); - else - intr_register_source(&pin->io_intsrc); - } - + if (pin->io_vector == 0 && mixed_mode_active && + mixed_mode_enabled) + ioapic_setup_mixed_mode(pin); + else + intr_register_source(&pin->io_intsrc); } } ==== //depot/projects/hammer/sys/amd64/amd64/legacy.c#11 (text+ko) ==== @@ -40,6 +40,7 @@ #include #include #include +#include #include #include #include @@ -221,17 +222,19 @@ atdev = malloc(sizeof(struct legacy_device), M_LEGACYDEV, M_NOWAIT | M_ZERO); - if (!atdev) - return(0); + if (atdev == NULL) + return(NULL); resource_list_init(&atdev->lg_resources); atdev->lg_pcibus = -1; - child = device_add_child_ordered(bus, order, name, unit); + child = device_add_child_ordered(bus, order, name, unit); + if (child == NULL) + free(atdev, M_LEGACYDEV); + else + /* should we free this in legacy_child_detached? */ + device_set_ivars(child, atdev); - /* should we free this in legacy_child_detached? */ - device_set_ivars(child, atdev); - - return(child); + return (child); } static int ==== //depot/projects/hammer/sys/amd64/amd64/mem.c#19 (text+ko) ==== @@ -50,6 +50,7 @@ #include #include #include +#include #include #include #include ==== //depot/projects/hammer/sys/amd64/amd64/mptable.c#26 (text+ko) ==== @@ -544,15 +544,10 @@ KASSERT(src_bus <= mptable_maxbusid, ("bus id %d too large", src_bus)); switch (busses[src_bus].bus_type) { case ISA: + case EISA: return (INTR_POLARITY_HIGH); case PCI: return (INTR_POLARITY_LOW); - case EISA: - KASSERT(src_bus_irq < 16, ("Invalid EISA IRQ %d", src_bus_irq)); - if (elcr_read_trigger(src_bus_irq) == INTR_TRIGGER_LEVEL) - return (INTR_POLARITY_LOW); - else - return (INTR_POLARITY_HIGH); default: panic("%s: unknown bus type %d", __func__, busses[src_bus].bus_type); ==== //depot/projects/hammer/sys/amd64/amd64/nexus.c#23 (text+ko) ==== @@ -481,8 +481,6 @@ struct resource_list_entry *rle; rle = resource_list_find(rl, type, rid); - device_printf(child, "type %d rid %d startp %p countp %p - got %p\n", - type, rid, startp, countp, rle); if (!rle) return(ENOENT); if (startp) ==== //depot/projects/hammer/sys/amd64/amd64/pmap.c#70 (text+ko) ==== ==== //depot/projects/hammer/sys/amd64/amd64/support.S#24 (text+ko) ==== ==== //depot/projects/hammer/sys/amd64/amd64/vm_machdep.c#43 (text+ko) ==== @@ -67,6 +67,7 @@ #include #include +#include #include #include ==== //depot/projects/hammer/sys/amd64/conf/GENERIC#42 (text+ko) ==== @@ -176,6 +176,7 @@ # PCI Ethernet NICs. device de # DEC/Intel DC21x4x (``Tulip'') device em # Intel PRO/1000 adapter Gigabit Ethernet Card +device ixgb # Intel PRO/10GbE Ethernet Card device txp # 3Com 3cR990 (``Typhoon'') device vx # 3Com 3c590, 3c595 (``Vortex'') ==== //depot/projects/hammer/sys/amd64/include/_stdint.h#6 (text+ko) ==== ==== //depot/projects/hammer/sys/amd64/include/cputypes.h#7 (text+ko) ==== @@ -44,11 +44,6 @@ #define CPU_SLEDGEHAMMER 2 /* AMD Sledgehammer */ #ifndef LOCORE -struct cpu_nameclass { - char *cpu_name; - int cpu_class; -}; - extern int cpu; extern int cpu_class; #endif ==== //depot/projects/hammer/sys/amd64/include/profile.h#18 (text+ko) ==== ==== //depot/projects/hammer/sys/amd64/isa/atpic.c#41 (text+ko) ==== @@ -43,6 +43,7 @@ #include #include #include +#include #include #include ==== //depot/projects/hammer/sys/amd64/isa/atpic_vector.S#20 (text+ko) ==== ==== //depot/projects/hammer/sys/amd64/isa/clock.c#24 (text+ko) ==== @@ -59,6 +59,7 @@ #include #include #include +#include #include #include #include ==== //depot/projects/hammer/sys/amd64/pci/pci_bus.c#20 (text+ko) ==== @@ -34,6 +34,7 @@ #include #include #include +#include #include #include