From owner-freebsd-alpha@FreeBSD.ORG Fri Sep 2 17:31:52 2005 Return-Path: X-Original-To: alpha@FreeBSD.org Delivered-To: freebsd-alpha@FreeBSD.ORG Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 5725516A420 for ; Fri, 2 Sep 2005 17:31:52 +0000 (GMT) (envelope-from jhb@FreeBSD.org) Received: from mv.twc.weather.com (mv.twc.weather.com [65.212.71.225]) by mx1.FreeBSD.org (Postfix) with ESMTP id AD0E843D46 for ; Fri, 2 Sep 2005 17:31:51 +0000 (GMT) (envelope-from jhb@FreeBSD.org) Received: from [10.50.40.201] (Not Verified[10.50.40.201]) by mv.twc.weather.com with NetIQ MailMarshal (v6, 0, 3, 8) id ; Fri, 02 Sep 2005 13:47:13 -0400 From: John Baldwin To: alpha@FreeBSD.org Date: Fri, 2 Sep 2005 13:24:13 -0400 User-Agent: KMail/1.8 MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200509021324.13391.jhb@FreeBSD.org> Cc: Subject: [PATCH] Add membar to bus dma PREWRITE operations X-BeenThere: freebsd-alpha@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to the Alpha List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 02 Sep 2005 17:31:52 -0000 The patch below adds a memory barrier to bus_dma PREWRITE operations to ensure that writes by the CPU to populate a buffer before it is read via DMA by a device will be completed before later writes by the CPU (later as in program order) to trigger the DMA. Please test! Patch should apply to 5.x and later. Thanks. --- //depot/vendor/freebsd/src/sys/alpha/alpha/busdma_machdep.c 2005/05/25 07:26:16 +++ //depot/user/jhb/acpipci/alpha/alpha/busdma_machdep.c 2005/08/18 17:55:22 @@ -891,6 +891,10 @@ } } } + + /* Ensure any pending writes have drained. */ + if (op & (BUS_DMASYNC_PREWRITE)) + alpha_mb(); } static void -- John Baldwin <>< http://www.FreeBSD.org/~jhb/ "Power Users Use the Power to Serve" = http://www.FreeBSD.org