From owner-svn-src-stable@freebsd.org Wed Nov 9 08:08:03 2016 Return-Path: Delivered-To: svn-src-stable@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id D35B3C37D4E; Wed, 9 Nov 2016 08:08:03 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 951EAB16; Wed, 9 Nov 2016 08:08:03 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id uA9882Ba059015; Wed, 9 Nov 2016 08:08:02 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id uA9882MM059014; Wed, 9 Nov 2016 08:08:02 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201611090808.uA9882MM059014@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Wed, 9 Nov 2016 08:08:02 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-11@freebsd.org Subject: svn commit: r308463 - stable/11/contrib/llvm/lib/Target/AArch64 X-SVN-Group: stable-11 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-stable@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for all the -stable branches of the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 09 Nov 2016 08:08:03 -0000 Author: dim Date: Wed Nov 9 08:08:02 2016 New Revision: 308463 URL: https://svnweb.freebsd.org/changeset/base/308463 Log: MFC r308375: Pull in r278002 from upstream llvm trunk (by Silviu Baranga): [AArch64] PR28877: Don't assume we're running after legalization when creating vcvtfp2fxs Summary: The DAG combine transformation that was generating the aarch64_neon_vcvtfp2fxs node was assuming that all inputs where legal and wasn't accounting that the input could be a v4f64 if we're trying to do the transformation before legalization. We now bail out in this case. All illegal types besides v4f64 were already rejected. Fixes https://llvm.org/bugs/show_bug.cgi?id=28877 Reviewers: jmolloy Subscribers: aemerson, rengolin, llvm-commits Differential Revision: https://reviews.llvm.org/D23261 This fixes several ports on AArch64. Requested by: andrew Modified: stable/11/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp Directory Properties: stable/11/ (props changed) Modified: stable/11/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp ============================================================================== --- stable/11/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp Wed Nov 9 07:31:39 2016 (r308462) +++ stable/11/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp Wed Nov 9 08:08:02 2016 (r308463) @@ -7562,6 +7562,7 @@ static SDValue performIntToFpCombine(SDN /// Fold a floating-point multiply by power of two into floating-point to /// fixed-point conversion. static SDValue performFpToIntCombine(SDNode *N, SelectionDAG &DAG, + TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) { if (!Subtarget->hasNEON()) return SDValue(); @@ -7604,10 +7605,16 @@ static SDValue performFpToIntCombine(SDN ResTy = FloatBits == 32 ? MVT::v2i32 : MVT::v2i64; break; case 4: - ResTy = MVT::v4i32; + ResTy = FloatBits == 32 ? MVT::v4i32 : MVT::v4i64; break; } + if (ResTy == MVT::v4i64 && DCI.isBeforeLegalizeOps()) + return SDValue(); + + assert((ResTy != MVT::v4i64 || DCI.isBeforeLegalizeOps()) && + "Illegal vector type after legalization"); + SDLoc DL(N); bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT; unsigned IntrinsicOpcode = IsSigned ? Intrinsic::aarch64_neon_vcvtfp2fxs @@ -9711,7 +9718,7 @@ SDValue AArch64TargetLowering::PerformDA return performIntToFpCombine(N, DAG, Subtarget); case ISD::FP_TO_SINT: case ISD::FP_TO_UINT: - return performFpToIntCombine(N, DAG, Subtarget); + return performFpToIntCombine(N, DAG, DCI, Subtarget); case ISD::FDIV: return performFDivCombine(N, DAG, Subtarget); case ISD::OR: