From owner-svn-ports-all@freebsd.org Thu Jan 17 23:27:13 2019 Return-Path: Delivered-To: svn-ports-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 2917F1483BEC; Thu, 17 Jan 2019 23:27:13 +0000 (UTC) (envelope-from swills@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) server-signature RSA-PSS (4096 bits) client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id C3C3D8ABF9; Thu, 17 Jan 2019 23:27:12 +0000 (UTC) (envelope-from swills@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id B7C7121606; Thu, 17 Jan 2019 23:27:12 +0000 (UTC) (envelope-from swills@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id x0HNRCYB040745; Thu, 17 Jan 2019 23:27:12 GMT (envelope-from swills@FreeBSD.org) Received: (from swills@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id x0HNRBol040741; Thu, 17 Jan 2019 23:27:11 GMT (envelope-from swills@FreeBSD.org) Message-Id: <201901172327.x0HNRBol040741@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: swills set sender to swills@FreeBSD.org using -f From: Steve Wills Date: Thu, 17 Jan 2019 23:27:11 +0000 (UTC) To: ports-committers@freebsd.org, svn-ports-all@freebsd.org, svn-ports-head@freebsd.org Subject: svn commit: r490609 - in head/cad: . verilator X-SVN-Group: ports-head X-SVN-Commit-Author: swills X-SVN-Commit-Paths: in head/cad: . verilator X-SVN-Commit-Revision: 490609 X-SVN-Commit-Repository: ports MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: C3C3D8ABF9 X-Spamd-Bar: -- Authentication-Results: mx1.freebsd.org X-Spamd-Result: default: False [-2.97 / 15.00]; local_wl_from(0.00)[FreeBSD.org]; NEURAL_HAM_MEDIUM(-1.00)[-0.999,0]; NEURAL_HAM_SHORT(-0.97)[-0.967,0]; NEURAL_HAM_LONG(-1.00)[-0.999,0]; ASN(0.00)[asn:11403, ipnet:2610:1c1:1::/48, country:US] X-BeenThere: svn-ports-all@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: SVN commit messages for the ports tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Jan 2019 23:27:13 -0000 Author: swills Date: Thu Jan 17 23:27:11 2019 New Revision: 490609 URL: https://svnweb.freebsd.org/changeset/ports/490609 Log: cad/verilator: create port Verilator is the fastest free Verilog HDL simulator, and beats most commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. WWW: https://www.veripool.org/projects/verilator/wiki/Intro PR: 230761 Submitted by: Kevin Zheng Added: head/cad/verilator/ head/cad/verilator/Makefile (contents, props changed) head/cad/verilator/distinfo (contents, props changed) head/cad/verilator/pkg-descr (contents, props changed) head/cad/verilator/pkg-plist (contents, props changed) Modified: head/cad/Makefile (contents, props changed) Modified: head/cad/Makefile ============================================================================== --- head/cad/Makefile Thu Jan 17 23:24:49 2019 (r490608) +++ head/cad/Makefile Thu Jan 17 23:27:11 2019 (r490609) @@ -101,6 +101,7 @@ SUBDIR += tochnog SUBDIR += transcalc SUBDIR += varkon + SUBDIR += verilator SUBDIR += verilog-mode.el SUBDIR += xcircuit SUBDIR += xtrkcad Added: head/cad/verilator/Makefile ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/cad/verilator/Makefile Thu Jan 17 23:27:11 2019 (r490609) @@ -0,0 +1,31 @@ +# $FreeBSD$ + +PORTNAME= verilator +PORTVERSION= 3.924 +CATEGORIES= cad +MASTER_SITES= https://www.veripool.org/ftp/ + +MAINTAINER= kevinz5000@gmail.com +COMMENT= Synthesizable Verilog to C++ compiler + +LICENSE= GPLv3 +LICENSE_FILE= ${WRKSRC}/COPYING + +BUILD_DEPENDS= flex:textproc/flex + +USES= bison gmake pathfix perl5 tar:tgz + +GNU_CONFIGURE= yes +CONFIGURE_ENV= INSTALL_PROGRAM="${INSTALL_SCRIPT}" + +post-patch: + ${REINPLACE_CMD} -e 's|@pkgconfigdir@|${PREFIX}/libdata/pkgconfig|' \ + ${WRKSRC}/Makefile.in + +post-build: + @${STRIP_CMD} ${WRKSRC}/bin/verilator_bin + +post-install: + ${RM} ${STAGEDIR}${PREFIX}/bin/verilator_bin_dbg ${STAGEDIR}${PREFIX}/bin/verilator_coverage_bin_dbg + +.include Added: head/cad/verilator/distinfo ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/cad/verilator/distinfo Thu Jan 17 23:27:11 2019 (r490609) @@ -0,0 +1,3 @@ +TIMESTAMP = 1534354040 +SHA256 (verilator-3.924.tgz) = 7dcb19711b8630ada59f0d3d7409faa9649e37bf4c53a0bbfcad32afb28b5975 +SIZE (verilator-3.924.tgz) = 2163952 Added: head/cad/verilator/pkg-descr ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/cad/verilator/pkg-descr Thu Jan 17 23:27:11 2019 (r490609) @@ -0,0 +1,8 @@ +Verilator is the fastest free Verilog HDL simulator, and beats most commercial +simulators. It compiles synthesizable Verilog (not test-bench code!), plus some +PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is +designed for large projects where fast simulation performance is of primary +concern, and is especially well suited to generate executable models of CPUs +for embedded software design teams. + +WWW: https://www.veripool.org/projects/verilator/wiki/Intro Added: head/cad/verilator/pkg-plist ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/cad/verilator/pkg-plist Thu Jan 17 23:27:11 2019 (r490609) @@ -0,0 +1,54 @@ +bin/verilator +bin/verilator_bin +bin/verilator_coverage +bin/verilator_profcfunc +libdata/pkgconfig/verilator.pc +man/man1/verilator.1.gz +man/man1/verilator_coverage.1.gz +man/man1/verilator_profcfunc.1.gz +%%DATADIR%%/bin/verilator_includer +%%DATADIR%%/examples/hello_world_c/Makefile +%%DATADIR%%/examples/hello_world_c/sim_main.cpp +%%DATADIR%%/examples/hello_world_c/top.v +%%DATADIR%%/examples/hello_world_sc/Makefile +%%DATADIR%%/examples/hello_world_sc/sc_main.cpp +%%DATADIR%%/examples/hello_world_sc/top.v +%%DATADIR%%/examples/tracing_c/Makefile +%%DATADIR%%/examples/tracing_c/Makefile_obj +%%DATADIR%%/examples/tracing_c/input.vc +%%DATADIR%%/examples/tracing_c/sim_main.cpp +%%DATADIR%%/examples/tracing_c/sub.v +%%DATADIR%%/examples/tracing_c/top.v +%%DATADIR%%/examples/tracing_sc/Makefile +%%DATADIR%%/examples/tracing_sc/Makefile_obj +%%DATADIR%%/examples/tracing_sc/input.vc +%%DATADIR%%/examples/tracing_sc/sc_main.cpp +%%DATADIR%%/examples/tracing_sc/sub.v +%%DATADIR%%/examples/tracing_sc/top.v +%%DATADIR%%/include/verilated.cpp +%%DATADIR%%/include/verilated.h +%%DATADIR%%/include/verilated.mk +%%DATADIR%%/include/verilated.v +%%DATADIR%%/include/verilated_config.h +%%DATADIR%%/include/verilated_config.h.in +%%DATADIR%%/include/verilated_cov.cpp +%%DATADIR%%/include/verilated_cov.h +%%DATADIR%%/include/verilated_cov_key.h +%%DATADIR%%/include/verilated_dpi.cpp +%%DATADIR%%/include/verilated_dpi.h +%%DATADIR%%/include/verilated_heavy.h +%%DATADIR%%/include/verilated_imp.h +%%DATADIR%%/include/verilated_save.cpp +%%DATADIR%%/include/verilated_save.h +%%DATADIR%%/include/verilated_sc.h +%%DATADIR%%/include/verilated_sym_props.h +%%DATADIR%%/include/verilated_syms.h +%%DATADIR%%/include/verilated_vcd_c.cpp +%%DATADIR%%/include/verilated_vcd_c.h +%%DATADIR%%/include/verilated_vcd_sc.cpp +%%DATADIR%%/include/verilated_vcd_sc.h +%%DATADIR%%/include/verilated_vpi.cpp +%%DATADIR%%/include/verilated_vpi.h +%%DATADIR%%/include/verilatedos.h +%%DATADIR%%/include/vltstd/svdpi.h +%%DATADIR%%/include/vltstd/vpi_user.h