From owner-svn-src-head@freebsd.org Mon Nov 21 15:42:55 2016 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id BA847C4DE10; Mon, 21 Nov 2016 15:42:55 +0000 (UTC) (envelope-from br@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 917D19DF; Mon, 21 Nov 2016 15:42:55 +0000 (UTC) (envelope-from br@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id uALFgsjg024869; Mon, 21 Nov 2016 15:42:54 GMT (envelope-from br@FreeBSD.org) Received: (from br@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id uALFgsV7024868; Mon, 21 Nov 2016 15:42:54 GMT (envelope-from br@FreeBSD.org) Message-Id: <201611211542.uALFgsV7024868@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: br set sender to br@FreeBSD.org using -f From: Ruslan Bukin Date: Mon, 21 Nov 2016 15:42:54 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r308928 - head/sys/mips/ingenic X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 21 Nov 2016 15:42:55 -0000 Author: br Date: Mon Nov 21 15:42:54 2016 New Revision: 308928 URL: https://svnweb.freebsd.org/changeset/base/308928 Log: Add PDMA controller registers. Obtained from: X1000 IoT Application Processor Programming Manual Sponsored by: DARPA, AFRL Added: head/sys/mips/ingenic/jz4780_pdma.h (contents, props changed) Added: head/sys/mips/ingenic/jz4780_pdma.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/mips/ingenic/jz4780_pdma.h Mon Nov 21 15:42:54 2016 (r308928) @@ -0,0 +1,68 @@ +/*- + * Copyright (c) 2016 Ruslan Bukin + * All rights reserved. + * + * This software was developed by SRI International and the University of + * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 + * ("CTSRD"), as part of the DARPA CRASH research programme. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* DMA Channel Registers */ +#define PDMA_DSA(n) (0x00 + 0x20 * n) /* Channel n Source Address */ +#define PDMA_DTA(n) (0x04 + 0x20 * n) /* Channel n Target Address */ +#define PDMA_DTC(n) (0x08 + 0x20 * n) /* Channel n Transfer Count */ +#define PDMA_DRT(n) (0x0C + 0x20 * n) /* Channel n Request Source */ +#define PDMA_DCS(n) (0x10 + 0x20 * n) /* Channel n Control/Status */ +#define PDMA_DCM(n) (0x14 + 0x20 * n) /* Channel n Command */ +#define PDMA_DDA(n) (0x18 + 0x20 * n) /* Channel n Descriptor Address */ +#define PDMA_DSD(n) (0x1C + 0x20 * n) /* Channel n Stride Difference */ + +/* Global Control Registers */ +#define PDMA_DMAC 0x1000 /* DMA Control */ +#define PDMA_DIRQP 0x1004 /* DMA Interrupt Pending */ +#define PDMA_DDB 0x1008 /* DMA Doorbell */ +#define PDMA_DDS 0x100C /* DMA Doorbell Set */ +#define PDMA_DIP 0x1010 /* Descriptor Interrupt Pending */ +#define PDMA_DIC 0x1014 /* Descriptor Interrupt Clear */ +#define PDMA_DMACP 0x101C /* DMA Channel Programmable */ +#define PDMA_DSIRQP 0x1020 /* Channel soft IRQ to MCU */ +#define PDMA_DSIRQM 0x1024 /* Channel soft IRQ mask */ +#define PDMA_DCIRQP 0x1028 /* Channel IRQ to MCU */ +#define PDMA_DCIRQM 0x102C /* Channel IRQ to MCU mask */ +#define PDMA_DMCS 0x1030 /* MCU Control and Status */ +#define PDMA_DMNMB 0x1034 /* MCU Normal Mailbox */ +#define PDMA_DMSMB 0x1038 /* MCU Security Mailbox */ +#define PDMA_DMINT 0x103C /* MCU Interrupt */ + +struct pdma_hwdesc { + uint32_t dcm; /* DMA Channel Command */ + uint32_t dsa; /* DMA Source Address */ + uint32_t dta; /* DMA Target Address */ + uint32_t dtc; /* DMA Transfer Counter */ + uint32_t sd; /* Stride Address */ + uint32_t drt; /* DMA Request Type */ + uint32_t reserved[2]; +};