Date: Wed, 30 May 2012 09:29:30 -0500 From: Zhihao Yuan <lichray@gmail.com> To: Michael Butler <imb@protected-networks.net> Cc: FreeBSD-STABLE Mailing List <freebsd-stable@freebsd.org> Subject: Re: Different features on different CPU cores?! Message-ID: <CAGsORuCdZWmDhYHdiDirpSBzXtv7%2BW2rVcfiXFBFzHgWxY1S7g@mail.gmail.com> In-Reply-To: <4FC62DDD.6060503@protected-networks.net> References: <CAGsORuBGpwuuozvob8TqnfPsAxaZYGpy4FPeGX2c9-K1RF3Qaw@mail.gmail.com> <4FC62DDD.6060503@protected-networks.net>
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On Wed, May 30, 2012 at 9:25 AM, Michael Butler
<imb@protected-networks.net> wrote:
>
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> On 05/30/12 10:15, Zhihao Yuan wrote:
>> Hi,
>>
>> Today I want to compile the latest www/chromium, and I found that I
>> encountered some SSSE3 problems, with either gcc46/clang, and I found
>> that this new version requires (S)SSE3 support.
>>
>> My CPU is a Intel i5 M 520, which suppose to support these. But when
>> I'm checking the CPU features, I see:
>>
>> CPU: Intel(R) Core(TM) i5 CPU M 520 @ 2.40GHz (2394.02-MHz K8-class CPU)
>> Origin =3D "GenuineIntel" Id =3D 0x20652 Family =3D 6 Model =3D 25 Stepp=
ing =3D 2
>> Features=3D0xbfebfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,P=
GE,MCA,CM
>> OV,PAT,PSE36,CLFLUSH,DTS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE>
>> Features2=3D0x298e3ff<SSE3,PCLMULQDQ,DTES64,MON,DS_CPL,VMX,SMX,EST,TM2,S=
SSE3,CX16
>> ,xTPR,PDCM,SSE4.1,SSE4.2,POPCNT,AESNI>
>>
>> What? Different features on different cores? Is it my CPU's problem or
>> FreeBSD's problem?
>>
> You are misreading this .. they ran out of bits in one word to describe
> the available features so they added another word 'features2' to
> describe the rest. These capabilities apply to both cores,
OK... I see what happened:
~> cc a.c
~> gcc46 a.c
In file included from a.c:1:0:
/usr/local/lib/gcc46/gcc/x86_64-portbld-freebsd8.3/4.6.3/include/pmmintrin.=
h:32:3:
error: #error "SSE3 instruction set not enabled"
~> clang a.c
In file included from a.c:1:
/usr/local/bin/../lib/clang/3.1/include/pmmintrin.h:28:2: error: "SSE3
instruction set not enabled"
#error "SSE3 instruction set not enabled"
^
1 error generated.
~> gcc46 -msse3 a.c
~> clang -msse3 a.c
~>
So the chromium port does not define -msse3/-mssse3 explicitly, so it
does not work with gcc46/clang.
>
> =C2=A0 =C2=A0imb
>
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--=20
Zhihao Yuan, nickname lichray
The best way to predict the future is to invent it.
___________________________________________________
4BSD -- http://4bsd.biz/
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