From owner-cvs-src@FreeBSD.ORG Tue Oct 18 14:48:53 2005 Return-Path: X-Original-To: cvs-src@FreeBSD.org Delivered-To: cvs-src@FreeBSD.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id B384816A41F; Tue, 18 Oct 2005 14:48:53 +0000 (GMT) (envelope-from gallatin@cs.duke.edu) Received: from duke.cs.duke.edu (duke.cs.duke.edu [152.3.140.1]) by mx1.FreeBSD.org (Postfix) with ESMTP id 093B443D46; Tue, 18 Oct 2005 14:48:52 +0000 (GMT) (envelope-from gallatin@cs.duke.edu) Received: from grasshopper.cs.duke.edu (grasshopper.cs.duke.edu [152.3.145.30]) by duke.cs.duke.edu (8.13.4/8.13.4) with ESMTP id j9IEmoQW018765 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 18 Oct 2005 10:48:50 -0400 (EDT) Received: (from gallatin@localhost) by grasshopper.cs.duke.edu (8.12.9p2/8.12.9/Submit) id j9IEmjtg029282; Tue, 18 Oct 2005 10:48:45 -0400 (EDT) (envelope-from gallatin) From: Andrew Gallatin MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Message-ID: <17237.2893.263419.610951@grasshopper.cs.duke.edu> Date: Tue, 18 Oct 2005 10:48:45 -0400 (EDT) To: Scott Long In-Reply-To: <4355080C.302@samsco.org> References: <200510172310.j9HNAVPL013057@repoman.freebsd.org> <20051018094402.A29138@grasshopper.cs.duke.edu> <435501B9.4070401@samsco.org> <17237.1482.52148.283282@grasshopper.cs.duke.edu> <4355080C.302@samsco.org> X-Mailer: VM 6.75 under 21.1 (patch 12) "Channel Islands" XEmacs Lucid Cc: cvs-src@FreeBSD.org, src-committers@FreeBSD.org, David Xu , cvs-all@FreeBSD.org Subject: Re: cvs commit: src/sys/amd64/amd64 cpu_switch.S machdep.c X-BeenThere: cvs-src@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: CVS commit messages for the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 18 Oct 2005 14:48:53 -0000 Scott Long writes: > Andrew Gallatin wrote: > > As I pointed out in another thread, both linux and solaris do it. > > Solaris seems to have a nice algorithm for keeping things in sync, and > > accounting for the TSC getting cleared after suspend/resume etc. At > > my level of understanding, this argument is nothing more than "but > > Mom, all the other kids are doing it". I was just hoping that > > somebody with real understanding could pick up on it. > > Steering mutliple TSC's together isn't that hard and there are plenty of > examples, as you point out. Accounting for the changes due to thermal > and power management (note that this isn't the same problem as suspend > and resume) is what worries me. Yes, I have no answer for this :( > > Yeah. I moved my back to hz=1000 when I noticed 4000 interrupts/sec > > on an idle system. > > > > Drew > > Do you mean 1000 or 100 here? Anyways, the high clock interrupt rate is Sorry.. That was a typo. I meant hz=100. Drew