From nobody Mon Oct 21 12:24:22 2024 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4XXDyH13Zjz5YwwH; Mon, 21 Oct 2024 12:24:23 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R11" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4XXDyG5tMrz4DqG; Mon, 21 Oct 2024 12:24:22 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1729513462; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=atdEdBb/mggeKgHa64HZLyGcZPLhb8nqzm3LsX0jU+s=; b=wdssz4rr1cijG6ejzWWoymEy/S1qos8M4yvLHH9oTL+csgczXU8lPnfWUvDqegZE3yfy+z Cey9yCKn+0wml8rNl4A8eDfx+6GZ6to9Gw4L9xXlRt2CaAfyOYvtmHrgT7Gzd4KGpAajPa YDWhZFU4RWpen/8CEbyMMRASrwrDURj9oxPzJsC85G9K2bFwxnvVOUcBDVoDR33szv8nXd YOn5YC/sie/mv//ZvXmkPNkgT/61dTY/9cW6ymeJffmA8GWL6dAWe59sgArjwk3nFceozZ 20dkKGkBV4WY3HW4KmSitK1Sz49ChysSpQbTcgF6BeHjfXj4zGcGQF6BTg/new== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1729513462; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=atdEdBb/mggeKgHa64HZLyGcZPLhb8nqzm3LsX0jU+s=; b=uY5v7jS25Mg/D6Oj1HS1TSUSeQ/hD0NQk9eJc7Xe5u+tYUDat62HNL09Kg2R1pRAclDfuH cvPrBsapmG5RwLMJsXsfwzzgSR7DTMueEgxT7imcgWM06SfOgK4hCfepRr8Xj4buMhc82M ETmGUVPG5p4LGdeNzKZmtqCBgY9ZtDEGRcHw4vm0vvnsUYNu3BQevtOEvtz9aIXKpShImG wpRrqFPYCK9pVRE6ZK561ZqDNq0ZpAN2bPlvmxlGO7iRfuZN4NJ0Bpa2sz/3dDostQe92m SZUQBj2wMCy2D1Obkzm0ONLAzFjfUOaYOXlD3pH5y5MY2zUVgALf7M8sC4aKqA== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1729513462; a=rsa-sha256; cv=none; b=UENBlPMcYSkLZCRrnNfX2j1CbXj5Sg8PrBJfgPKtt64dB+pwPjeWIjMXWt8R2/LGI/zCEX Ehw4P9CME5QSeTnJIVBGmMHjmZnjrKty/fpV2m+GUyFxmss3msgO/4Ks7AF35QCBRqaVPy XGoAElx8ZvgrmCrzHiLPWsaVnlbW3SmrLGOWt8doZYRhBj0TCJN2gwbCv8nhwfD/6jn1Ou wRJwFaqh7ZKr1+8dcPHSfM2KkL7mVUVwqEjXjuxIguJyW1PtqNe4DwVzjtdfXKkOprVOEX qVsJVDUbf7U/6YQmNnRfP86uzftq4zWaxMaxzLdFQq8hd0KnK7aRciYJ7j5jLA== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4XXDyG5TKczTMV; Mon, 21 Oct 2024 12:24:22 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.18.1/8.18.1) with ESMTP id 49LCOMli049217; Mon, 21 Oct 2024 12:24:22 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.18.1/8.18.1/Submit) id 49LCOM4E049214; Mon, 21 Oct 2024 12:24:22 GMT (envelope-from git) Date: Mon, 21 Oct 2024 12:24:22 GMT Message-Id: <202410211224.49LCOM4E049214@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Andrew Turner Subject: git: 5727c249ad2a - main - arm64: Use register types to build kernel ID regs List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-all@freebsd.org Sender: owner-dev-commits-src-all@FreeBSD.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: andrew X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 5727c249ad2a94cf726c8db60841cf2112245cb3 Auto-Submitted: auto-generated The branch main has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=5727c249ad2a94cf726c8db60841cf2112245cb3 commit 5727c249ad2a94cf726c8db60841cf2112245cb3 Author: Andrew Turner AuthorDate: 2024-10-18 09:17:15 +0000 Commit: Andrew Turner CommitDate: 2024-10-21 12:23:15 +0000 arm64: Use register types to build kernel ID regs Use the ID register tables to find how to adjust the ID register fields in the kernel and vmm views. This allows us to use the same method to get a common view of CTR_EL0. Reviewed by: imp Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D47125 --- sys/arm64/arm64/identcpu.c | 34 ++++++++-------------------------- 1 file changed, 8 insertions(+), 26 deletions(-) diff --git a/sys/arm64/arm64/identcpu.c b/sys/arm64/arm64/identcpu.c index 7c5fdc04fdc7..834b0c5493b4 100644 --- a/sys/arm64/arm64/identcpu.c +++ b/sys/arm64/arm64/identcpu.c @@ -78,6 +78,8 @@ SYSCTL_INT(_machdep_cache, OID_AUTO, allow_idc, CTLFLAG_RDTUN, &allow_idc, 0, static void check_cpu_regs(u_int cpu, struct cpu_desc *desc, struct cpu_desc *prev_desc); +static uint64_t update_special_reg_field(uint64_t user_reg, u_int type, + uint64_t value, u_int width, u_int shift, bool sign); /* * The default implementation of I-cache sync assumes we have an @@ -2181,27 +2183,6 @@ mrs_field_cmp(uint64_t a, uint64_t b, u_int shift, int width, bool sign) return (a - b); } -static uint64_t -update_lower_register(uint64_t val, uint64_t new_val, u_int shift, - int width, bool sign) -{ - uint64_t mask; - - KASSERT(width > 0 && width < 64, ("%s: Invalid width %d", __func__, - width)); - - /* - * If the new value is less than the existing value update it. - */ - if (mrs_field_cmp(new_val, val, shift, width, sign) < 0) { - mask = (1ul << width) - 1; - val &= ~(mask << shift); - val |= new_val & (mask << shift); - } - - return (val); -} - bool extract_user_id_field(u_int reg, u_int field_shift, uint8_t *val) { @@ -2249,9 +2230,9 @@ get_kernel_reg_masked(u_int reg, uint64_t *valp, uint64_t mask) val = CPU_DESC_FIELD(kern_cpu_desc, i); fields = user_regs[i].fields; for (int j = 0; fields[j].type != 0; j++) { - mask = update_lower_register(mask, val, - fields[j].shift, fields[j].width, - fields[j].sign); + mask = update_special_reg_field(mask, + fields[j].type, val, fields[j].width, + fields[j].shift, fields[j].sign); } *valp = mask; return (true); @@ -2357,8 +2338,9 @@ update_special_regs(u_int cpu) fields[j].sign); /* Update the kernel ID register view */ - kern_reg = update_lower_register(kern_reg, value, - fields[j].shift, fields[j].width, fields[j].sign); + kern_reg = update_special_reg_field(kern_reg, + fields[j].type, value, fields[j].width, + fields[j].shift, fields[j].sign); } CPU_DESC_FIELD(kern_cpu_desc, i) = kern_reg;