From nobody Mon Jan 26 15:57:45 2026 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4f0CqG0c1tz6QRgN for ; Mon, 26 Jan 2026 15:57:46 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R13" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4f0CqF6Jmmz453N for ; Mon, 26 Jan 2026 15:57:45 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1769443065; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=PKyDlU1coTH7SFgHU5YAeBYT1N4+5lVW+WfVwH9oCbI=; b=aKDkOpDhn4PBveFYg9ZrOJ9r957Yy5gDSwi3cObXcE7zM8RziOjyaYSF4LL0u2/NH+HX/1 Kyc+UZHVCkSsUSZ5GJmfd6DXD4SIc3iEb1IIaLvVn6cF0qBJXSTPqhat8cBjAvDJ5P9UD4 +IfULKYpdAEswZtY8GWP7W7fcv0YO+1KKJp9DfmL5WDjyqYGQGa4EnEKZzgfdSPWzN40d5 fw7qEwxVYDmnhvp+Mp955TfBJKlEs/sAQeinGfylNfVuFDmvpfvm0u0RnmVTPjgr/ujoJ3 FQF/xcTsO3u426ZQ4lE4EWu9cJLtpus1tGcBpuy/Fsnt+OGJXddpvI4RaLpvHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1769443065; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=PKyDlU1coTH7SFgHU5YAeBYT1N4+5lVW+WfVwH9oCbI=; b=sDmTfmHoMJgd62aq/rIDaAFdxc301DfLZZLOH8ebt6uB/xtz9+cxTt5HAzmRDMQ7z/p4dZ YI/tbRclFYcWjfKapXR01AuS8rjvRmmUlDokT9ZJSDqX61HxOrrjE6q0z1miYBQ5yMk8aL 6UsIZfOyg0KLiNIm45vzwXM04asgUrMJXe48KzttUvZ8tCdnuJlediFBIL1p3nMoXTzpTC uMF8q7f3Cy7M4aO3bc4lG6DRKm83goXTEflAaMi41Jt+OHU97phjKPb2Z+QGezfCiB1Urq LivmLLZLRYTPmbKLpvqe7zcPG3aHpFkj5k/UsA8ljd2t1upC9jymgCcfcH3EMA== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1769443065; a=rsa-sha256; cv=none; b=LXc1+I7VofkSAp/ipWp4xDnDqe5SJBHh9fq063X8w/HuX9Y8Gv5JfZy0XHZkA0MGqfw1uw VNezIo/c4pcW1cc5nI/AuPMDZqk8uzaNJk+KVJJSyeXGrir8aRd0eqgSpxWPwEgyJO1F5P u/IxSHAjR6K4qa2J8Czpk0ixCmPoTJ0MbXIpnHAo5mO+Pbei9w3Kx6P4PK7lPb8wE4clOK 04IQfRA3aaTE2Azi0E7pey5b+0WJl2eiTREw2MKl/QYRP9z63UT3OHW66ahf385VLk7ay8 nBUixsxJzeJ7PlpF34BqUYz1CwjX3Axnd93En2QtAUldHqmIy1XlgXW3lXBsyA== ARC-Authentication-Results: i=1; mx1.freebsd.org; none Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) by mxrelay.nyi.freebsd.org (Postfix) with ESMTP id 4f0CqF5n3MzBvm for ; Mon, 26 Jan 2026 15:57:45 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from git (uid 1279) (envelope-from git@FreeBSD.org) id 39b4d by gitrepo.freebsd.org (DragonFly Mail Agent v0.13+ on gitrepo.freebsd.org); Mon, 26 Jan 2026 15:57:45 +0000 To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Marius Strobl Subject: git: e769bc771843 - main - sym(4): Employ memory barriers also on x86 List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-all@freebsd.org Sender: owner-dev-commits-src-all@FreeBSD.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: marius X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: e769bc77184312b6137a9b180c97b87c0760b849 Auto-Submitted: auto-generated Date: Mon, 26 Jan 2026 15:57:45 +0000 Message-Id: <69778ef9.39b4d.5c480abe@gitrepo.freebsd.org> The branch main has been updated by marius: URL: https://cgit.FreeBSD.org/src/commit/?id=e769bc77184312b6137a9b180c97b87c0760b849 commit e769bc77184312b6137a9b180c97b87c0760b849 Author: Marius Strobl AuthorDate: 2026-01-26 13:58:57 +0000 Commit: Marius Strobl CommitDate: 2026-01-26 15:54:48 +0000 sym(4): Employ memory barriers also on x86 In an MP world, it doesn't hold that x86 requires no memory barriers. This change should also fix panics due to out-of-sync data seen with FreeBSD VMs on top of OpenStack and HBAs of type lsiLogic. [1] While at it: - Improve the granularity somewhat by distinguishing between read and write memory barriers as well as refer to existing *mb(9) functions instead of duplicating these [2], unless IO barriers are also used. - Nuke the unused SYM_DRIVER_NAME macro. PR: 270816 [1] Obtained from: BSD-licensed Linux sym53c8xx driver [2] MFC after: 1 week --- sys/dev/sym/sym_hipd.c | 42 +++++++++++++++--------------------------- 1 file changed, 15 insertions(+), 27 deletions(-) diff --git a/sys/dev/sym/sym_hipd.c b/sys/dev/sym/sym_hipd.c index 0e51607fb07a..f78d595a73ce 100644 --- a/sys/dev/sym/sym_hipd.c +++ b/sys/dev/sym/sym_hipd.c @@ -58,7 +58,6 @@ */ #include -#define SYM_DRIVER_NAME "sym-1.6.5-20000902" /* #define SYM_DEBUG_GENERIC_SUPPORT */ @@ -114,27 +113,16 @@ typedef u_int32_t u32; #include /* - * IA32 architecture does not reorder STORES and prevents - * LOADS from passing STORES. It is called `program order' - * by Intel and allows device drivers to deal with memory - * ordering by only ensuring that the code is not reordered - * by the compiler when ordering is required. - * Other architectures implement a weaker ordering that - * requires memory barriers (and also IO barriers when they - * make sense) to be used. - */ -#if defined __i386__ || defined __amd64__ -#define MEMORY_BARRIER() do { ; } while(0) -#elif defined __powerpc__ -#define MEMORY_BARRIER() __asm__ volatile("eieio; sync" : : : "memory") -#elif defined __arm__ -#define MEMORY_BARRIER() dmb() -#elif defined __aarch64__ -#define MEMORY_BARRIER() dmb(sy) -#elif defined __riscv -#define MEMORY_BARRIER() fence() + * Architectures may implement weak ordering that requires memory barriers + * to be used for LOADS and STORES to become globally visible (and also IO + * barriers when they make sense). + */ +#ifdef __powerpc__ +#define MEMORY_READ_BARRIER() __asm__ volatile("eieio; sync" : : : "memory") +#define MEMORY_WRITE_BARRIER() MEMORY_READ_BARRIER() #else -#error "Not supported platform" +#define MEMORY_READ_BARRIER() rmb() +#define MEMORY_WRITE_BARRIER() wmb() #endif /* @@ -892,13 +880,13 @@ struct sym_nvram { */ #define OUTL_DSP(v) \ do { \ - MEMORY_BARRIER(); \ + MEMORY_WRITE_BARRIER(); \ OUTL (nc_dsp, (v)); \ } while (0) #define OUTONB_STD() \ do { \ - MEMORY_BARRIER(); \ + MEMORY_WRITE_BARRIER(); \ OUTONB (nc_dcntl, (STD|NOCOM)); \ } while (0) @@ -2908,7 +2896,7 @@ static void sym_put_start_queue(hcb_p np, ccb_p cp) if (qidx >= MAX_QUEUE*2) qidx = 0; np->squeue [qidx] = cpu_to_scr(np->idletask_ba); - MEMORY_BARRIER(); + MEMORY_WRITE_BARRIER(); np->squeue [np->squeueput] = cpu_to_scr(cp->ccb_ba); np->squeueput = qidx; @@ -2920,7 +2908,7 @@ static void sym_put_start_queue(hcb_p np, ccb_p cp) * Script processor may be waiting for reselect. * Wake it up. */ - MEMORY_BARRIER(); + MEMORY_WRITE_BARRIER(); OUTB (nc_istat, SIGP|np->istat_sem); } @@ -3061,7 +3049,7 @@ static int sym_wakeup_done (hcb_p np) cp = sym_ccb_from_dsa(np, dsa); if (cp) { - MEMORY_BARRIER(); + MEMORY_READ_BARRIER(); sym_complete_ok (np, cp); ++n; } else @@ -3859,7 +3847,7 @@ static void sym_intr1 (hcb_p np) * On paper, a memory barrier may be needed here. * And since we are paranoid ... :) */ - MEMORY_BARRIER(); + MEMORY_READ_BARRIER(); /* * First, interrupts we want to service cleanly.