From owner-svn-src-head@freebsd.org Mon Jan 6 20:58:00 2020 Return-Path: Delivered-To: svn-src-head@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id 185B41EDE03; Mon, 6 Jan 2020 20:58:00 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) server-signature RSA-PSS (4096 bits) client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 47s7Bb6zRHz4CRB; Mon, 6 Jan 2020 20:57:59 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id EAC1C1C305; Mon, 6 Jan 2020 20:57:59 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id 006KvxWi058190; Mon, 6 Jan 2020 20:57:59 GMT (envelope-from andrew@FreeBSD.org) Received: (from andrew@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id 006KvxZC058188; Mon, 6 Jan 2020 20:57:59 GMT (envelope-from andrew@FreeBSD.org) Message-Id: <202001062057.006KvxZC058188@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: andrew set sender to andrew@FreeBSD.org using -f From: Andrew Turner Date: Mon, 6 Jan 2020 20:57:59 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r356426 - in head/sys/arm64: arm64 include X-SVN-Group: head X-SVN-Commit-Author: andrew X-SVN-Commit-Paths: in head/sys/arm64: arm64 include X-SVN-Commit-Revision: 356426 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 06 Jan 2020 20:58:00 -0000 Author: andrew Date: Mon Jan 6 20:57:59 2020 New Revision: 356426 URL: https://svnweb.freebsd.org/changeset/base/356426 Log: Add more Arm arm64 CPU identification values - Add all the Cortex-A CPU ID register values I can find. - Add the Neoverse-N1 ID regiser value [1] - Sort macros by register value. PR: 243065 Submitted by: Ali Saidi [1] Sponsored by: DARPA, AFRL (other than [1]) Modified: head/sys/arm64/arm64/identcpu.c head/sys/arm64/include/cpu.h Modified: head/sys/arm64/arm64/identcpu.c ============================================================================== --- head/sys/arm64/arm64/identcpu.c Mon Jan 6 19:47:59 2020 (r356425) +++ head/sys/arm64/arm64/identcpu.c Mon Jan 6 20:57:59 2020 (r356426) @@ -156,9 +156,14 @@ static const struct cpu_parts cpu_parts_arm[] = { { CPU_PART_CORTEX_A53, "Cortex-A53" }, { CPU_PART_CORTEX_A55, "Cortex-A55" }, { CPU_PART_CORTEX_A57, "Cortex-A57" }, + { CPU_PART_CORTEX_A65, "Cortex-A65" }, { CPU_PART_CORTEX_A72, "Cortex-A72" }, { CPU_PART_CORTEX_A73, "Cortex-A73" }, { CPU_PART_CORTEX_A75, "Cortex-A75" }, + { CPU_PART_CORTEX_A76, "Cortex-A76" }, + { CPU_PART_CORTEX_A76AE, "Cortex-A76AE" }, + { CPU_PART_CORTEX_A77, "Cortex-A77" }, + { CPU_PART_NEOVERSE_N1, "Neoverse-N1" }, CPU_PART_NONE, }; /* Cavium */ Modified: head/sys/arm64/include/cpu.h ============================================================================== --- head/sys/arm64/include/cpu.h Mon Jan 6 19:47:59 2020 (r356425) +++ head/sys/arm64/include/cpu.h Mon Jan 6 20:57:59 2020 (r356426) @@ -81,13 +81,18 @@ /* ARM Part numbers */ #define CPU_PART_FOUNDATION 0xD00 -#define CPU_PART_CORTEX_A35 0xD04 #define CPU_PART_CORTEX_A53 0xD03 +#define CPU_PART_CORTEX_A35 0xD04 #define CPU_PART_CORTEX_A55 0xD05 +#define CPU_PART_CORTEX_A65 0xD06 #define CPU_PART_CORTEX_A57 0xD07 #define CPU_PART_CORTEX_A72 0xD08 #define CPU_PART_CORTEX_A73 0xD09 #define CPU_PART_CORTEX_A75 0xD0A +#define CPU_PART_CORTEX_A76 0xD0B +#define CPU_PART_NEOVERSE_N1 0xD0C +#define CPU_PART_CORTEX_A77 0xD0D +#define CPU_PART_CORTEX_A76AE 0xD0E /* Cavium Part numbers */ #define CPU_PART_THUNDERX 0x0A1