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[209.85.222.175]) by smtp.gmail.com with ESMTPSA id i28sm11001074qtc.57.2020.03.02.09.14.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 02 Mar 2020 09:14:04 -0800 (PST) Received: by mail-qk1-f175.google.com with SMTP id u124so333978qkh.13; Mon, 02 Mar 2020 09:14:04 -0800 (PST) X-Received: by 2002:a05:620a:2116:: with SMTP id l22mr241302qkl.311.1583169244181; Mon, 02 Mar 2020 09:14:04 -0800 (PST) MIME-Version: 1.0 References: <202002281832.01SIWaEL071685@repo.freebsd.org> <5767791583138727@sas1-c7aad230fe87.qloud-c.yandex.net> In-Reply-To: <5767791583138727@sas1-c7aad230fe87.qloud-c.yandex.net> From: Ryan Libby Date: Mon, 2 Mar 2020 09:13:53 -0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: svn commit: r358439 - head/sys/amd64/include To: "Alexander V. Chernikov" Cc: "src-committers@freebsd.org" , "svn-src-all@freebsd.org" , "svn-src-head@freebsd.org" Content-Type: text/plain; charset="UTF-8" X-Rspamd-Queue-Id: 48WRZT558Jz4TLT X-Spamd-Bar: --- Authentication-Results: mx1.freebsd.org; dkim=none; dmarc=none; spf=pass (mx1.freebsd.org: domain of rlibby@gmail.com designates 209.85.222.170 as permitted sender) smtp.mailfrom=rlibby@gmail.com X-Spamd-Result: default: False [-3.45 / 15.00]; ARC_NA(0.00)[]; TO_DN_EQ_ADDR_SOME(0.00)[]; RCVD_TLS_ALL(0.00)[]; FROM_HAS_DN(0.00)[]; RCPT_COUNT_THREE(0.00)[4]; R_SPF_ALLOW(-0.20)[+ip4:209.85.128.0/17:c]; NEURAL_HAM_LONG(-1.00)[-1.000,0]; MIME_GOOD(-0.10)[text/plain]; DMARC_NA(0.00)[freebsd.org]; RCVD_VIA_SMTP_AUTH(0.00)[]; TO_DN_SOME(0.00)[]; RCVD_COUNT_THREE(0.00)[4]; TO_MATCH_ENVRCPT_SOME(0.00)[]; RCVD_IN_DNSWL_NONE(0.00)[170.222.85.209.list.dnswl.org : 127.0.5.0]; NEURAL_HAM_MEDIUM(-1.00)[-1.000,0]; IP_SCORE(-1.45)[ip: (-2.54), ipnet: 209.85.128.0/17(-2.99), asn: 15169(-1.66), country: US(-0.05)]; FORGED_SENDER(0.30)[rlibby@freebsd.org,rlibby@gmail.com]; RWL_MAILSPIKE_POSSIBLE(0.00)[170.222.85.209.rep.mailspike.net : 127.0.0.17]; MIME_TRACE(0.00)[0:+]; R_DKIM_NA(0.00)[]; FREEMAIL_ENVFROM(0.00)[gmail.com]; ASN(0.00)[asn:15169, ipnet:209.85.128.0/17, country:US]; FROM_NEQ_ENVFROM(0.00)[rlibby@freebsd.org,rlibby@gmail.com] X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Mar 2020 17:14:11 -0000 On Mon, Mar 2, 2020 at 12:45 AM Alexander V. Chernikov wrote: > > 28.02.2020, 18:32, "Ryan Libby" : > > Author: rlibby > > Date: Fri Feb 28 18:32:36 2020 > > New Revision: 358439 > > URL: https://svnweb.freebsd.org/changeset/base/358439 > > > > Log: > > amd64 atomic.h: minor codegen optimization in flag access > > > > Previously the pattern to extract status flags from inline assembly > > blocks was to use setcc in the block to write the flag to a register. > > This was suboptimal in a few ways: > > - It would lead to code like: sete %cl; test %cl; jne, i.e. a flag > > would just be loaded into a register and then reloaded to a flag. > > - The setcc would force the block to use an additional register. > > - If the client code didn't care for the flag value then the setcc > > would be entirely pointless but could not be eliminated by the > > optimizer. > > > > A more modern inline asm construct (since gcc 6 and clang 9) allows for > This effectively restricts kernel builds by all older compilers. > Is there any chance of making it conditional depending on the compiler version/features? Yes, it is possible to test for __GCC_ASM_FLAG_OUTPUTS__. It is more maintenance effort going forward. If building current with an old cross compiler is an important scenario, we can either revert this and the following revision or work up a patch to make it conditional. I'll see what that might look like. > > "flag output operands", where a C variable can be written directly from > > a flag. The optimizer can then use this to produce direct code where > > the flag does not take a trip through a register. > > > > In practice this makes each affected operation sequence shorter by five > > bytes of instructions. It's unlikely this has a measurable performance > > impact. > > > > Reviewed by: kib, markj, mjg > > Sponsored by: Dell EMC Isilon > > Differential Revision: https://reviews.freebsd.org/D23869 > > > > Modified: > > head/sys/amd64/include/atomic.h > > > > Modified: head/sys/amd64/include/atomic.h > > ============================================================================== > > --- head/sys/amd64/include/atomic.h Fri Feb 28 17:41:46 2020 (r358438) > > +++ head/sys/amd64/include/atomic.h Fri Feb 28 18:32:36 2020 (r358439) > > @@ -201,9 +201,8 @@ atomic_cmpset_##TYPE(volatile u_##TYPE *dst, u_##TYPE > > __asm __volatile( \ > > " " MPLOCKED " " \ > > " cmpxchg %3,%1 ; " \ > > - " sete %0 ; " \ > > "# atomic_cmpset_" #TYPE " " \ > > - : "=q" (res), /* 0 */ \ > > + : "=@cce" (res), /* 0 */ \ > > "+m" (*dst), /* 1 */ \ > > "+a" (expect) /* 2 */ \ > > : "r" (src) /* 3 */ \ > > @@ -219,9 +218,8 @@ atomic_fcmpset_##TYPE(volatile u_##TYPE *dst, u_##TYPE > > __asm __volatile( \ > > " " MPLOCKED " " \ > > " cmpxchg %3,%1 ; " \ > > - " sete %0 ; " \ > > "# atomic_fcmpset_" #TYPE " " \ > > - : "=q" (res), /* 0 */ \ > > + : "=@cce" (res), /* 0 */ \ > > "+m" (*dst), /* 1 */ \ > > "+a" (*expect) /* 2 */ \ > > : "r" (src) /* 3 */ \ > > @@ -278,9 +276,8 @@ atomic_testandset_int(volatile u_int *p, u_int v) > > __asm __volatile( > > " " MPLOCKED " " > > " btsl %2,%1 ; " > > - " setc %0 ; " > > "# atomic_testandset_int" > > - : "=q" (res), /* 0 */ > > + : "=@ccc" (res), /* 0 */ > > "+m" (*p) /* 1 */ > > : "Ir" (v & 0x1f) /* 2 */ > > : "cc"); > > @@ -295,9 +292,8 @@ atomic_testandset_long(volatile u_long *p, u_int v) > > __asm __volatile( > > " " MPLOCKED " " > > " btsq %2,%1 ; " > > - " setc %0 ; " > > "# atomic_testandset_long" > > - : "=q" (res), /* 0 */ > > + : "=@ccc" (res), /* 0 */ > > "+m" (*p) /* 1 */ > > : "Jr" ((u_long)(v & 0x3f)) /* 2 */ > > : "cc"); > > @@ -312,9 +308,8 @@ atomic_testandclear_int(volatile u_int *p, u_int v) > > __asm __volatile( > > " " MPLOCKED " " > > " btrl %2,%1 ; " > > - " setc %0 ; " > > "# atomic_testandclear_int" > > - : "=q" (res), /* 0 */ > > + : "=@ccc" (res), /* 0 */ > > "+m" (*p) /* 1 */ > > : "Ir" (v & 0x1f) /* 2 */ > > : "cc"); > > @@ -329,9 +324,8 @@ atomic_testandclear_long(volatile u_long *p, u_int v) > > __asm __volatile( > > " " MPLOCKED " " > > " btrq %2,%1 ; " > > - " setc %0 ; " > > "# atomic_testandclear_long" > > - : "=q" (res), /* 0 */ > > + : "=@ccc" (res), /* 0 */ > > "+m" (*p) /* 1 */ > > : "Jr" ((u_long)(v & 0x3f)) /* 2 */ > > : "cc");