Date: Mon, 29 Jan 1996 14:36:55 -0700 (MST) From: Terry Lambert <terry@lambert.org> To: luigi@labinfo.iet.unipi.it (Luigi Rizzo) Cc: hasty@rah.star-gate.com, terry@lambert.org, jkh@time.cdrom.com, james@miller.cs.uwm.edu, dufault@hda.com, hackers@FreeBSD.org, multimedia@rah.star-gate.com Subject: Re: [FCC Warning!] The Dangerous effect of Direct TV !! Message-ID: <199601292136.OAA04613@phaeton.artisoft.com> In-Reply-To: <199601290803.JAA04923@labinfo.iet.unipi.it> from "Luigi Rizzo" at Jan 29, 96 09:03:15 am
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> Consider a few things: > > * why should the VRAM be cacheable in the first place, given that the > video chipset is doing all sorts of things on it. It probably shouldn't. How do you tell the system to not cache it and be obeyed if you have a Cyrix/TI? How about a HiNT? An old OPTi chipset? > * often both the grabber and the video board are on the same PCI bus. This is a good thing. > * every location is written by the grabber only once per frame. This is, however, irrelvant. > * one frame does not fit into 256K of cache I have 512k of cache. This also neglects things like MPEG delta transfers instead of full frame copies (though you personally might not be interested in playing mpeg data the same way, I am). > --> we should not bother too much about the problem mentioned by Terry. I just mention it because it occurred to me it might be a problem; that there isn't an answer is OK with me, but it shouldn't be ignored unless it's been ruled out. That doesn't mean bothering with it now. Note that the bus-master/cache interaction could be a problem for frame grab DMA into the machine rather than direct to the video card for cards that don't support mapping as linear frame buffers. Terry Lambert terry@lambert.org --- Any opinions in this posting are my own and not those of my present or previous employers.
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