From owner-freebsd-mips@FreeBSD.ORG Thu Sep 29 14:27:59 2011 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 994C0106566B; Thu, 29 Sep 2011 14:27:59 +0000 (UTC) (envelope-from aduane@juniper.net) Received: from exprod7og125.obsmtp.com (exprod7og125.obsmtp.com [64.18.2.28]) by mx1.freebsd.org (Postfix) with ESMTP id 180E68FC0A; Thu, 29 Sep 2011 14:27:58 +0000 (UTC) Received: from P-EMHUB03-HQ.jnpr.net ([66.129.224.36]) (using TLSv1) by exprod7ob125.postini.com ([64.18.6.12]) with SMTP ID DSNKToSAbrQ/NpMF6PX79F7Z5m2D1vKo17L/@postini.com; Thu, 29 Sep 2011 07:27:59 PDT Received: from p-emfe02-wf.jnpr.net (172.28.145.25) by P-EMHUB03-HQ.jnpr.net (172.24.192.37) with Microsoft SMTP Server (TLS) id 8.3.83.0; Thu, 29 Sep 2011 07:12:48 -0700 Received: from EMBX01-WF.jnpr.net ([fe80::8002:d3e7:4146:af5f]) by p-emfe02-wf.jnpr.net ([fe80::c126:c633:d2dc:8090%11]) with mapi; Thu, 29 Sep 2011 10:12:47 -0400 From: Andrew Duane To: Jayachandran C. , Adrian Chadd Date: Thu, 29 Sep 2011 10:12:46 -0400 Thread-Topic: eventtimer issue on mips: temporary workaround Thread-Index: Acx+cuSpRZVi5xNTS/apx6gBZwXIvAAPomSQ Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Cc: "freebsd-mips@freebsd.org" Subject: RE: eventtimer issue on mips: temporary workaround X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 29 Sep 2011 14:27:59 -0000 I've been running JC's patch on my Octeon blade for a while, and it does fi= x some serious problems. It's been very stable. As to why "wait" wouldn't just return if an interrupt is asserted, I don't = know. The MIPS manual is (deliberately?) vague on these details, but any so= ftware engineer can explain why that's needed to write correct software. Ma= ybe the silicon engineers didn't listen? =A0................................... Andrew Duane Juniper Networks o=A0=A0=A0+1 978 589 0551 m=A0 +1 603-770-7088 aduane@juniper.net =A0 > -----Original Message----- > From: owner-freebsd-mips@freebsd.org [mailto:owner-freebsd- > mips@freebsd.org] On Behalf Of Jayachandran C. > Sent: Wednesday, September 28, 2011 11:42 PM > To: Adrian Chadd > Cc: freebsd-mips@freebsd.org > Subject: Re: eventtimer issue on mips: temporary workaround >=20 > On Wed, Sep 28, 2011 at 10:06 PM, Adrian Chadd > wrote: > > .. so, the patch is totallyw rong. > > > > intr_disable() needs to be moved before critical_enter() or it > doesn't > > achieve anything. >=20 > I'm not able to figure out why... >=20 > > But the race is still there, between intr_enable() and "wait". > > The only way to eliminate this race is to completely eliminate all > the > > code in cpu_idle(). >=20 > the amd implementation seems to be using the STI instruction to enable > interrupts - but I'm not able to see how to avoid this race condition > on platforms which does not have a similar instruction. >=20 > > Would someone clued in the implementation of wait please step up and > help? :) >=20 > What if go back to the earlier version of cpu_idle which does not have > critical_enter() and cpu_idleclock() for now, or does this also have > issues? >=20 > I had also seen issues on XLR which went away when I took out > 'ET_FLAGS_ONESHOT' from the mips clock event timer . That is another > possible workaround. >=20 > JC. > _______________________________________________ > freebsd-mips@freebsd.org mailing list > http://lists.freebsd.org/mailman/listinfo/freebsd-mips > To unsubscribe, send any mail to "freebsd-mips-unsubscribe@freebsd.org"