From owner-svn-ports-head@FreeBSD.ORG Thu Sep 5 17:39:26 2013 Return-Path: Delivered-To: svn-ports-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTP id 42B2E11B; Thu, 5 Sep 2013 17:39:26 +0000 (UTC) (envelope-from nox@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id 220EA2347; Thu, 5 Sep 2013 17:39:26 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.7/8.14.7) with ESMTP id r85HdPtv083370; Thu, 5 Sep 2013 17:39:26 GMT (envelope-from nox@svn.freebsd.org) Received: (from nox@localhost) by svn.freebsd.org (8.14.7/8.14.5/Submit) id r85HdPNk083368; Thu, 5 Sep 2013 17:39:25 GMT (envelope-from nox@svn.freebsd.org) Message-Id: <201309051739.r85HdPNk083368@svn.freebsd.org> From: Juergen Lock Date: Thu, 5 Sep 2013 17:39:25 +0000 (UTC) To: ports-committers@freebsd.org, svn-ports-all@freebsd.org, svn-ports-head@freebsd.org Subject: svn commit: r326423 - in head/emulators/qemu-devel: . files X-SVN-Group: ports-head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-ports-head@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: SVN commit messages for the ports tree for head List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Sep 2013 17:39:26 -0000 Author: nox Date: Thu Sep 5 17:39:25 2013 New Revision: 326423 URL: http://svnweb.freebsd.org/changeset/ports/326423 Log: - Add patch to fix pcnet-pci NIC big endian guests like MIPS Malta: [1] http://lists.nongnu.org/archive/html/qemu-stable/2013-08/msg00217.html See also gonzo's blog post: http://kernelnomicon.org/?p=401 - Bump PORTREVISION. Submitted by: gonzo (via irc) [1] Obtained from: qemu upstream [1] Added: head/emulators/qemu-devel/files/patch-hw-net-pcnet-pci.c (contents, props changed) Modified: head/emulators/qemu-devel/Makefile Modified: head/emulators/qemu-devel/Makefile ============================================================================== --- head/emulators/qemu-devel/Makefile Thu Sep 5 17:37:22 2013 (r326422) +++ head/emulators/qemu-devel/Makefile Thu Sep 5 17:39:25 2013 (r326423) @@ -3,6 +3,7 @@ PORTNAME= qemu PORTVERSION= 1.6.0 +PORTREVISION= 1 CATEGORIES= emulators MASTER_SITES= http://wiki.qemu.org/download/:release \ LOCAL/nox:snapshot Added: head/emulators/qemu-devel/files/patch-hw-net-pcnet-pci.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/emulators/qemu-devel/files/patch-hw-net-pcnet-pci.c Thu Sep 5 17:39:25 2013 (r326423) @@ -0,0 +1,48 @@ +From: aurelien@aurel32.net (Aurelien Jarno) +Subject: [Qemu-devel] [PATCH] pcnet-pci: mark I/O and MMIO as LITTLE_ENDIAN +Date: Wed, 28 Aug 2013 14:17:39 +0200 +Message-ID: <1377692259-19959-1-git-send-email-aurelien@aurel32.net> +To: qemu-devel@nongnu.org +Cc: Paolo Bonzini , qemu-stable@nongnu.org, + Aurelien Jarno + +Now that the memory subsystem is propagating the endianness correctly, +the pcnet-pci device should have its I/O ports and MMIO memory marked +as LITTLE_ENDIAN, as PCI devices are little endian. + +This makes the pcnet-pci NIC to work again on big endian MIPS Malta +(default NIC). + +Cc: qemu-stable@nongnu.org +Signed-off-by: Aurelien Jarno +--- + hw/net/pcnet-pci.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/hw/net/pcnet-pci.c b/hw/net/pcnet-pci.c +index a893165..865f2f0 100644 +--- a/hw/net/pcnet-pci.c ++++ b/hw/net/pcnet-pci.c +@@ -134,7 +134,7 @@ static void pcnet_ioport_write(void *opaque, hwaddr addr, + static const MemoryRegionOps pcnet_io_ops = { + .read = pcnet_ioport_read, + .write = pcnet_ioport_write, +- .endianness = DEVICE_NATIVE_ENDIAN, ++ .endianness = DEVICE_LITTLE_ENDIAN, + }; + + static void pcnet_mmio_writeb(void *opaque, hwaddr addr, uint32_t val) +@@ -256,7 +256,7 @@ static const MemoryRegionOps pcnet_mmio_ops = { + .read = { pcnet_mmio_readb, pcnet_mmio_readw, pcnet_mmio_readl }, + .write = { pcnet_mmio_writeb, pcnet_mmio_writew, pcnet_mmio_writel }, + }, +- .endianness = DEVICE_NATIVE_ENDIAN, ++ .endianness = DEVICE_LITTLE_ENDIAN, + }; + + static void pci_physical_memory_write(void *dma_opaque, hwaddr addr, +-- +1.7.10.4 + + +