Date: Sun, 8 Jan 2023 09:40:57 GMT From: Yuri Victorovich <yuri@FreeBSD.org> To: ports-committers@FreeBSD.org, dev-commits-ports-all@FreeBSD.org, dev-commits-ports-main@FreeBSD.org Subject: git: 019de3fad32a - main - cad/py-vunit-hdl: New pert: Open source unit testing framework for VHDL/SystemVerilog Message-ID: <202301080940.3089evbu011147@gitrepo.freebsd.org>
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The branch main has been updated by yuri: URL: https://cgit.FreeBSD.org/ports/commit/?id=019de3fad32a6d0d433f7fe672555c1e46479716 commit 019de3fad32a6d0d433f7fe672555c1e46479716 Author: Yuri Victorovich <yuri@FreeBSD.org> AuthorDate: 2023-01-08 08:47:46 +0000 Commit: Yuri Victorovich <yuri@FreeBSD.org> CommitDate: 2023-01-08 09:40:50 +0000 cad/py-vunit-hdl: New pert: Open source unit testing framework for VHDL/SystemVerilog --- cad/Makefile | 1 + cad/py-vunit-hdl/Makefile | 21 +++++++++++++++++++++ cad/py-vunit-hdl/distinfo | 3 +++ cad/py-vunit-hdl/pkg-descr | 5 +++++ 4 files changed, 30 insertions(+) diff --git a/cad/Makefile b/cad/Makefile index eb78c22e670e..9ac5b05745f3 100644 --- a/cad/Makefile +++ b/cad/Makefile @@ -111,6 +111,7 @@ SUBDIR += py-pyfda SUBDIR += py-pygmsh SUBDIR += py-pymtl + SUBDIR += py-vunit-hdl SUBDIR += python-gdsii SUBDIR += qcad SUBDIR += qcsxcad diff --git a/cad/py-vunit-hdl/Makefile b/cad/py-vunit-hdl/Makefile new file mode 100644 index 000000000000..71c7d9bf9eb6 --- /dev/null +++ b/cad/py-vunit-hdl/Makefile @@ -0,0 +1,21 @@ +PORTNAME= vunit-hdl +DISTVERSION= 4.6.0 +CATEGORIES= cad python +MASTER_SITES= CHEESESHOP +PKGNAMEPREFIX= ${PYTHON_PKGNAMEPREFIX} +DISTNAME= ${PORTNAME:S/-/_/}-${PORTVERSION} + +MAINTAINER= yuri@FreeBSD.org +COMMENT= Open source unit testing framework for VHDL/SystemVerilog +WWW= https://vunit.github.io/ + +LICENSE= MPL20 + +RUN_DEPENDS= ${PYTHON_PKGNAMEPREFIX}colorama>0:devel/py-colorama@${PY_FLAVOR} + +USES= python:3.6+ +USE_PYTHON= distutils autoplist pytest # 2 tests fail, see https://github.com/VUnit/vunit/issues/886 + +NO_ARCH= yes + +.include <bsd.port.mk> diff --git a/cad/py-vunit-hdl/distinfo b/cad/py-vunit-hdl/distinfo new file mode 100644 index 000000000000..4a36e544fc44 --- /dev/null +++ b/cad/py-vunit-hdl/distinfo @@ -0,0 +1,3 @@ +TIMESTAMP = 1673167323 +SHA256 (vunit_hdl-4.6.0.tar.gz) = b405a97b5da4c26c99d8c726f38594c9173c0ac3f8a0832431c8e4920d2cacdf +SIZE (vunit_hdl-4.6.0.tar.gz) = 626992 diff --git a/cad/py-vunit-hdl/pkg-descr b/cad/py-vunit-hdl/pkg-descr new file mode 100644 index 000000000000..2c5b8b031639 --- /dev/null +++ b/cad/py-vunit-hdl/pkg-descr @@ -0,0 +1,5 @@ +VUnit is an open source unit testing framework for VHDL/SystemVerilog. It +features the functionality needed to realize continuous and automated +testing of your HDL code. VUnit doesn't replace but rather complements +traditional testing methodologies by supporting a test early and often +approach through automation. Read more about VUnit.
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