From owner-svn-src-all@freebsd.org Fri Mar 3 23:08:44 2017 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id BB2D6CF7167; Fri, 3 Mar 2017 23:08:44 +0000 (UTC) (envelope-from avg@FreeBSD.org) Received: from citapm.icyb.net.ua (citapm.icyb.net.ua [212.40.38.140]) by mx1.freebsd.org (Postfix) with ESMTP id 9F0401C5C; Fri, 3 Mar 2017 23:08:43 +0000 (UTC) (envelope-from avg@FreeBSD.org) Received: from porto.starpoint.kiev.ua (porto-e.starpoint.kiev.ua [212.40.38.100]) by citapm.icyb.net.ua (8.8.8p3/ICyb-2.3exp) with ESMTP id BAA28002; Sat, 04 Mar 2017 01:08:35 +0200 (EET) (envelope-from avg@FreeBSD.org) Received: from localhost ([127.0.0.1]) by porto.starpoint.kiev.ua with esmtp (Exim 4.34 (FreeBSD)) id 1cjwJP-000AIg-Ol; Sat, 04 Mar 2017 01:08:35 +0200 Subject: Re: svn commit: r314636 - in head/sys/x86: include x86 To: src-committers@FreeBSD.org, svn-src-all@FreeBSD.org, svn-src-head@FreeBSD.org References: <201703032242.v23Mghiv020834@repo.freebsd.org> From: Andriy Gapon Message-ID: <3129f8b1-3552-022b-66d7-88600950b8c0@FreeBSD.org> Date: Sat, 4 Mar 2017 01:07:59 +0200 User-Agent: Mozilla/5.0 (X11; FreeBSD amd64; rv:45.0) Gecko/20100101 Thunderbird/45.6.0 MIME-Version: 1.0 In-Reply-To: <201703032242.v23Mghiv020834@repo.freebsd.org> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 03 Mar 2017 23:08:44 -0000 On 04/03/2017 00:42, Andriy Gapon wrote: > Author: avg > Date: Fri Mar 3 22:42:43 2017 > New Revision: 314636 > URL: https://svnweb.freebsd.org/changeset/base/314636 > > Log: > MCA: add AMD Error Thresholding support > > Currently the feature is implemented only for a subset of errors > reported via Bank 4. The subset includes only DRAM-related errors. > > The new code builds upon and reuses the Intel CMC (Correctable MCE > Counters) support code. However, the AMD feature is quite different > and, unfortunately, much less regular. > > For references please see AMD BKDGs for models 10h - 16h. > Specifically, see MSR0000_0413 NB Machine Check Misc (Thresholding) > Register (MC4_MISC0). > http://developer.amd.com/resources/developer-guides-manuals/ > AMD processors from the new family 17h (Ryzen) are said to implement somehting called Scalable MCA which is different from both Error Thresholding and Intel CMC. That's not supported, because no technical documentation is released at the moment. -- Andriy Gapon