Date: Sat, 4 Mar 2017 01:07:59 +0200 From: Andriy Gapon <avg@FreeBSD.org> To: src-committers@FreeBSD.org, svn-src-all@FreeBSD.org, svn-src-head@FreeBSD.org Subject: Re: svn commit: r314636 - in head/sys/x86: include x86 Message-ID: <3129f8b1-3552-022b-66d7-88600950b8c0@FreeBSD.org> In-Reply-To: <201703032242.v23Mghiv020834@repo.freebsd.org> References: <201703032242.v23Mghiv020834@repo.freebsd.org>
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On 04/03/2017 00:42, Andriy Gapon wrote: > Author: avg > Date: Fri Mar 3 22:42:43 2017 > New Revision: 314636 > URL: https://svnweb.freebsd.org/changeset/base/314636 > > Log: > MCA: add AMD Error Thresholding support > > Currently the feature is implemented only for a subset of errors > reported via Bank 4. The subset includes only DRAM-related errors. > > The new code builds upon and reuses the Intel CMC (Correctable MCE > Counters) support code. However, the AMD feature is quite different > and, unfortunately, much less regular. > > For references please see AMD BKDGs for models 10h - 16h. > Specifically, see MSR0000_0413 NB Machine Check Misc (Thresholding) > Register (MC4_MISC0). > http://developer.amd.com/resources/developer-guides-manuals/ > AMD processors from the new family 17h (Ryzen) are said to implement somehting called Scalable MCA which is different from both Error Thresholding and Intel CMC. That's not supported, because no technical documentation is released at the moment. -- Andriy Gapon
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